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[ARM] 4202/2: S3C2443: IRQ sub source handlers
Add IRQ handlers for the IRQs which originate from the sub-interrupt register on the S3C2443 Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
90bc8566fb
commit
72262e8b19
@ -39,12 +39,12 @@
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#include <asm/plat-s3c24xx/pm.h>
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#include <asm/plat-s3c24xx/irq.h>
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/* WDT/AC97 */
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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static void s3c_irq_demux_wdtac97(unsigned int irq,
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struct irq_desc *desc)
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static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
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{
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unsigned int subsrc, submsk;
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unsigned int end;
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struct irq_desc *mydesc;
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/* read the current pending interrupts, and the mask
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@ -53,63 +53,199 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 27;
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subsrc &= 3;
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subsrc &= ~submsk;
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subsrc >>= (irq - S3C2410_IRQSUB(0));
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subsrc &= (1 << len)-1;
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if (subsrc != 0) {
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if (subsrc & 1) {
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mydesc = irq_desc + IRQ_S3C2443_WDT;
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desc_handle_irq(IRQ_S3C2443_WDT, mydesc);
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}
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if (subsrc & 2) {
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mydesc = irq_desc + IRQ_S3C2443_AC97;
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desc_handle_irq(IRQ_S3C2443_AC97, mydesc);
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}
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end = len + irq;
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mydesc = irq_desc + irq;
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for (; irq < end && subsrc; irq++) {
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if (subsrc & 1)
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desc_handle_irq(irq, mydesc);
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mydesc++;
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subsrc >>= 1;
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}
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}
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/* WDT/AC97 sub interrupts */
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#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
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static void
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s3c_irq_wdtac97_mask(unsigned int irqno)
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static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<27);
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s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
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}
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static void
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s3c_irq_wdtac97_unmask(unsigned int irqno)
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#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
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#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
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static void s3c2443_irq_wdtac97_mask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_WDT);
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s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static void
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s3c_irq_wdtac97_ack(unsigned int irqno)
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static void s3c2443_irq_wdtac97_unmask(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<27);
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s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
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}
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static struct irq_chip s3c_irq_wdtac97 = {
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.mask = s3c_irq_wdtac97_mask,
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.unmask = s3c_irq_wdtac97_unmask,
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.ack = s3c_irq_wdtac97_ack,
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static void s3c2443_irq_wdtac97_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static struct irq_chip s3c2443_irq_wdtac97 = {
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.mask = s3c2443_irq_wdtac97_mask,
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.unmask = s3c2443_irq_wdtac97_unmask,
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.ack = s3c2443_irq_wdtac97_ack,
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};
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static int s3c2443_irq_add(struct sys_device *sysdev)
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/* LCD sub interrupts */
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static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
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}
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#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
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#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
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static void s3c2443_irq_lcd_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
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}
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static void s3c2443_irq_lcd_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_LCD);
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}
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static void s3c2443_irq_lcd_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
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}
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static struct irq_chip s3c2443_irq_lcd = {
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.mask = s3c2443_irq_lcd_mask,
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.unmask = s3c2443_irq_lcd_unmask,
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.ack = s3c2443_irq_lcd_ack,
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};
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/* DMA sub interrupts */
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static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_DMA1, 6);
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}
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#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
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#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
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static void s3c2443_irq_dma_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
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}
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static void s3c2443_irq_dma_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_DMA);
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}
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static void s3c2443_irq_dma_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
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}
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static struct irq_chip s3c2443_irq_dma = {
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.mask = s3c2443_irq_dma_mask,
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.unmask = s3c2443_irq_dma_unmask,
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.ack = s3c2443_irq_dma_ack,
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};
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/* UART3 sub interrupts */
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static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_UART3, 3);
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}
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#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
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#define SUBMSK_UART3 (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
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static void s3c2443_irq_uart3_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
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}
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static void s3c2443_irq_uart3_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_UART3);
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}
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static void s3c2443_irq_uart3_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
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}
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static struct irq_chip s3c2443_irq_uart3 = {
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.mask = s3c2443_irq_uart3_mask,
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.unmask = s3c2443_irq_uart3_unmask,
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.ack = s3c2443_irq_uart3_ack,
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};
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/* CAM sub interrupts */
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static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
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}
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#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
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#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
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static void s3c2443_irq_cam_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM);
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}
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static void s3c2443_irq_cam_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_CAM);
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}
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static void s3c2443_irq_cam_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM);
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}
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static struct irq_chip s3c2443_irq_cam = {
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.mask = s3c2443_irq_cam_mask,
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.unmask = s3c2443_irq_cam_unmask,
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.ack = s3c2443_irq_cam_ack,
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};
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/* IRQ initialisation code */
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static int __init s3c2443_add_sub(unsigned int base,
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void (*demux)(unsigned int,
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struct irq_desc *),
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struct irq_chip *chip,
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unsigned int start, unsigned int end)
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{
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unsigned int irqno;
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printk("S3C2443: IRQ Support\n");
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set_irq_chip(base, &s3c_irq_level_chip);
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set_irq_handler(base, handle_level_irq);
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set_irq_chained_handler(base, demux);
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/* add new chained handler for wdt, ac7 */
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set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
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set_irq_handler(IRQ_WDT, handle_level_irq);
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set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
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for (irqno = IRQ_S3C2443_WDT; irqno <= IRQ_S3C2443_AC97; irqno++) {
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set_irq_chip(irqno, &s3c_irq_wdtac97);
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for (irqno = start; irqno <= end; irqno++) {
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set_irq_chip(irqno, chip);
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set_irq_handler(irqno, handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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@ -117,6 +253,30 @@ static int s3c2443_irq_add(struct sys_device *sysdev)
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return 0;
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}
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static int s3c2443_irq_add(struct sys_device *sysdev)
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{
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printk("S3C2443: IRQ Support\n");
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s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
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IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
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s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
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IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
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s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
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&s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
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s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
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&s3c2443_irq_uart3,
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IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
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s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
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&s3c2443_irq_wdtac97,
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IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
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return 0;
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}
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static struct sysdev_driver s3c2443_irq_driver = {
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.add = s3c2443_irq_add,
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};
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