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drm/amdgpu/display: Add core dc support for DCN

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Core display support for DCN.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2017-05-08 15:19:06 -04:00 committed by Alex Deucher
parent 74c49c7ac1
commit 70ccab6040
17 changed files with 11467 additions and 0 deletions
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10
drivers/gpu/drm/amd/display/dc/dcn10/Makefile Normal file
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#
# Makefile for DCN.
DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
dcn10_transform.o dcn10_opp.o dcn10_timing_generator.o \
dcn10_mem_input.o dcn10_mpc.o
AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)

1866
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c Normal file
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38
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h Normal file
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_HWSS_DCN10_H__
#define __DC_HWSS_DCN10_H__
#include "core_types.h"
struct core_dc;
bool dcn10_hw_sequencer_construct(struct core_dc *dc);
extern void fill_display_configs(
const struct validate_context *context,
struct dm_pp_display_configuration *pp_display_cfg);
#endif /* __DC_HWSS_DCN10_H__ */

883
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c Normal file
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dcn10_ipp.h"
#include "reg_helper.h"
#define REG(reg) \
(ippn10->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
#define CTX \
ippn10->base.ctx
struct dcn10_input_csc_matrix {
enum dc_color_space color_space;
uint32_t regval[12];
};
static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
{COLOR_SPACE_SRGB,
{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{COLOR_SPACE_SRGB_LIMITED,
{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{COLOR_SPACE_YCBCR601,
{0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
0, 0x2000, 0x38b4, 0xe3a6} },
{COLOR_SPACE_YCBCR601_LIMITED,
{0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
0, 0x2568, 0x40de, 0xdd3a} },
{COLOR_SPACE_YCBCR709,
{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
0x2000, 0x3b61, 0xe24f} },
{COLOR_SPACE_YCBCR709_LIMITED,
{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
0x2568, 0x43ee, 0xdbb2} }
};
enum dcn10_input_csc_select {
INPUT_CSC_SELECT_BYPASS = 0,
INPUT_CSC_SELECT_ICSC,
INPUT_CSC_SELECT_COMA
};
static void dcn10_program_input_csc(
struct input_pixel_processor *ipp,
enum dc_color_space color_space,
enum dcn10_input_csc_select select)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
int i;
int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
const uint32_t *regval = NULL;
uint32_t selection = 1;
if (select == INPUT_CSC_SELECT_BYPASS) {
REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
return;
}
for (i = 0; i < arr_size; i++)
if (dcn10_input_csc_matrix[i].color_space == color_space) {
regval = dcn10_input_csc_matrix[i].regval;
break;
}
if (regval == NULL) {
BREAK_TO_DEBUGGER();
return;
}
if (select == INPUT_CSC_SELECT_COMA)
selection = 2;
REG_SET(CM_ICSC_CONTROL, 0,
CM_ICSC_MODE, selection);
if (select == INPUT_CSC_SELECT_ICSC) {
/*R*/
REG_SET_2(CM_ICSC_C11_C12, 0,
CM_ICSC_C11, regval[0],
CM_ICSC_C12, regval[1]);
regval += 2;
REG_SET_2(CM_ICSC_C13_C14, 0,
CM_ICSC_C13, regval[0],
CM_ICSC_C14, regval[1]);
/*G*/
regval += 2;
REG_SET_2(CM_ICSC_C21_C22, 0,
CM_ICSC_C21, regval[0],
CM_ICSC_C22, regval[1]);
regval += 2;
REG_SET_2(CM_ICSC_C23_C24, 0,
CM_ICSC_C23, regval[0],
CM_ICSC_C24, regval[1]);
/*B*/
regval += 2;
REG_SET_2(CM_ICSC_C31_C32, 0,
CM_ICSC_C31, regval[0],
CM_ICSC_C32, regval[1]);
regval += 2;
REG_SET_2(CM_ICSC_C33_C34, 0,
CM_ICSC_C33, regval[0],
CM_ICSC_C34, regval[1]);
} else {
/*R*/
REG_SET_2(CM_COMA_C11_C12, 0,
CM_COMA_C11, regval[0],
CM_COMA_C12, regval[1]);
regval += 2;
REG_SET_2(CM_COMA_C13_C14, 0,
CM_COMA_C13, regval[0],
CM_COMA_C14, regval[1]);
/*G*/
regval += 2;
REG_SET_2(CM_COMA_C21_C22, 0,
CM_COMA_C21, regval[0],
CM_COMA_C22, regval[1]);
regval += 2;
REG_SET_2(CM_COMA_C23_C24, 0,
CM_COMA_C23, regval[0],
CM_COMA_C24, regval[1]);
/*B*/
regval += 2;
REG_SET_2(CM_COMA_C31_C32, 0,
CM_COMA_C31, regval[0],
CM_COMA_C32, regval[1]);
regval += 2;
REG_SET_2(CM_COMA_C33_C34, 0,
CM_COMA_C33, regval[0],
CM_COMA_C34, regval[1]);
}
}
/*program de gamma RAM B*/
static void dcn10_ipp_program_degamma_lutb_settings(
struct input_pixel_processor *ipp,
const struct pwl_params *params)
{
const struct gamma_curve *curve;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
REG_SET_2(CM_DGAM_RAMB_START_CNTL_B, 0,
CM_DGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0);
REG_SET_2(CM_DGAM_RAMB_START_CNTL_G, 0,
CM_DGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0);
REG_SET_2(CM_DGAM_RAMB_START_CNTL_R, 0,
CM_DGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0);
REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_B, 0,
CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_G, 0,
CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_R, 0,
CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
REG_SET(CM_DGAM_RAMB_END_CNTL1_B, 0,
CM_DGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
REG_SET_2(CM_DGAM_RAMB_END_CNTL2_B, 0,
CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y,
CM_DGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope);
REG_SET(CM_DGAM_RAMB_END_CNTL1_G, 0,
CM_DGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
REG_SET_2(CM_DGAM_RAMB_END_CNTL2_G, 0,
CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y,
CM_DGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope);
REG_SET(CM_DGAM_RAMB_END_CNTL1_R, 0,
CM_DGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
REG_SET_2(CM_DGAM_RAMB_END_CNTL2_R, 0,
CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y,
CM_DGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope);
curve = params->arr_curve_points;
REG_SET_4(CM_DGAM_RAMB_REGION_0_1, 0,
CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_2_3, 0,
CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_4_5, 0,
CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_6_7, 0,
CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_8_9, 0,
CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_10_11, 0,
CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_12_13, 0,
CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMB_REGION_14_15, 0,
CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
}
/*program de gamma RAM A*/
static void dcn10_ipp_program_degamma_luta_settings(
struct input_pixel_processor *ipp,
const struct pwl_params *params)
{
const struct gamma_curve *curve;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
REG_SET_2(CM_DGAM_RAMA_START_CNTL_B, 0,
CM_DGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0);
REG_SET_2(CM_DGAM_RAMA_START_CNTL_G, 0,
CM_DGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0);
REG_SET_2(CM_DGAM_RAMA_START_CNTL_R, 0,
CM_DGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0);
REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_B, 0,
CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_G, 0,
CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_R, 0,
CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
REG_SET(CM_DGAM_RAMA_END_CNTL1_B, 0,
CM_DGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
REG_SET_2(CM_DGAM_RAMA_END_CNTL2_B, 0,
CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y,
CM_DGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope);
REG_SET(CM_DGAM_RAMA_END_CNTL1_G, 0,
CM_DGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
REG_SET_2(CM_DGAM_RAMA_END_CNTL2_G, 0,
CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y,
CM_DGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope);
REG_SET(CM_DGAM_RAMA_END_CNTL1_R, 0,
CM_DGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
REG_SET_2(CM_DGAM_RAMA_END_CNTL2_R, 0,
CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y,
CM_DGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope);
curve = params->arr_curve_points;
REG_SET_4(CM_DGAM_RAMA_REGION_0_1, 0,
CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_2_3, 0,
CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_4_5, 0,
CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_6_7, 0,
CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_8_9, 0,
CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_10_11, 0,
CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_12_13, 0,
CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_DGAM_RAMA_REGION_14_15, 0,
CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
}
static void ipp_power_on_degamma_lut(
struct input_pixel_processor *ipp,
bool power_on)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
REG_SET(CM_MEM_PWR_CTRL, 0,
SHARED_MEM_PWR_DIS, power_on == true ? 0:1);
}
static void ipp_program_degamma_lut(
struct input_pixel_processor *ipp,
const struct pwl_result_data *rgb,
uint32_t num,
bool is_ram_a)
{
uint32_t i;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
CM_DGAM_LUT_WRITE_EN_MASK, 7);
REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
is_ram_a == true ? 0:1);
REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
for (i = 0 ; i < num; i++) {
REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
REG_SET(CM_DGAM_LUT_DATA, 0,
CM_DGAM_LUT_DATA, rgb[i].delta_red_reg);
REG_SET(CM_DGAM_LUT_DATA, 0,
CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(CM_DGAM_LUT_DATA, 0,
CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
}
}
static void dcn10_ipp_enable_cm_block(
struct input_pixel_processor *ipp)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
}
static void dcn10_ipp_full_bypass(struct input_pixel_processor *ipp)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
/* Input pixel format: ARGB8888 */
REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
CNVC_SURFACE_PIXEL_FORMAT, 0x8);
/* Zero expansion */
REG_SET_3(FORMAT_CONTROL, 0,
CNVC_BYPASS, 0,
ALPHA_EN, 0,
FORMAT_EXPANSION_MODE, 0);
/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
/* Setting degamma bypass for now */
REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0);
}
static void dcn10_ipp_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
dcn10_ipp_enable_cm_block(ipp);
switch (mode) {
case IPP_DEGAMMA_MODE_BYPASS:
/* Setting de gamma bypass for now */
REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
break;
case IPP_DEGAMMA_MODE_HW_sRGB:
REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
break;
case IPP_DEGAMMA_MODE_HW_xvYCC:
REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
break;
default:
BREAK_TO_DEBUGGER();
break;
}
}
static bool dcn10_cursor_program_control(
struct dcn10_ipp *ippn10,
bool pixel_data_invert,
enum dc_cursor_color_format color_format)
{
REG_SET_2(CURSOR_SETTINS, 0,
/* no shift of the cursor HDL schedule */
CURSOR0_DST_Y_OFFSET, 0,
/* used to shift the cursor chunk request deadline */
CURSOR0_CHUNK_HDL_ADJUST, 3);
REG_UPDATE_2(CURSOR0_CONTROL,
CUR0_MODE, color_format,
CUR0_INVERT_MODE, 0);
if (color_format == CURSOR_MODE_MONO) {
/* todo: clarify what to program these to */
REG_UPDATE(CURSOR0_COLOR0,
CUR0_COLOR0, 0x00000000);
REG_UPDATE(CURSOR0_COLOR1,
CUR0_COLOR1, 0xFFFFFFFF);
}
/* TODO: Fixed vs float */
REG_UPDATE_3(FORMAT_CONTROL,
CNVC_BYPASS, 0,
ALPHA_EN, 1,
FORMAT_EXPANSION_MODE, 0);
REG_UPDATE(CURSOR0_CONTROL,
CUR0_EXPANSION_MODE, 0);
if (0 /*attributes->attribute_flags.bits.MIN_MAX_INVERT*/) {
REG_UPDATE(CURSOR0_CONTROL,
CUR0_MAX,
0 /* TODO */);
REG_UPDATE(CURSOR0_CONTROL,
CUR0_MIN,
0 /* TODO */);
}
return true;
}
enum cursor_pitch {
CURSOR_PITCH_64_PIXELS = 0,
CURSOR_PITCH_128_PIXELS,
CURSOR_PITCH_256_PIXELS
};
enum cursor_lines_per_chunk {
CURSOR_LINE_PER_CHUNK_2 = 1,
CURSOR_LINE_PER_CHUNK_4,
CURSOR_LINE_PER_CHUNK_8,
CURSOR_LINE_PER_CHUNK_16
};
static enum cursor_pitch dcn10_get_cursor_pitch(
unsigned int pitch)
{
enum cursor_pitch hw_pitch;
switch (pitch) {
case 64:
hw_pitch = CURSOR_PITCH_64_PIXELS;
break;
case 128:
hw_pitch = CURSOR_PITCH_128_PIXELS;
break;
case 256:
hw_pitch = CURSOR_PITCH_256_PIXELS;
break;
default:
DC_ERR("Invalid cursor pitch of %d. "
"Only 64/128/256 is supported on DCN.\n", pitch);
hw_pitch = CURSOR_PITCH_64_PIXELS;
break;
}
return hw_pitch;
}
static enum cursor_lines_per_chunk dcn10_get_lines_per_chunk(
unsigned int cur_width,
enum dc_cursor_color_format format)
{
enum cursor_lines_per_chunk line_per_chunk;
if (format == CURSOR_MODE_MONO)
/* impl B. expansion in CUR Buffer reader */
line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
else if (cur_width <= 32)
line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
else if (cur_width <= 64)
line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
else if (cur_width <= 128)
line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
else
line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
return line_per_chunk;
}
static void dcn10_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attr)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
enum cursor_pitch hw_pitch = dcn10_get_cursor_pitch(attr->pitch);
enum cursor_lines_per_chunk lpc = dcn10_get_lines_per_chunk(
attr->width, attr->color_format);
ippn10->curs_attr = *attr;
REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
REG_UPDATE(CURSOR_SURFACE_ADDRESS,
CURSOR_SURFACE_ADDRESS, attr->address.low_part);
REG_UPDATE_2(CURSOR_SIZE,
CURSOR_WIDTH, attr->width,
CURSOR_HEIGHT, attr->height);
REG_UPDATE_3(CURSOR_CONTROL,
CURSOR_MODE, attr->color_format,
CURSOR_PITCH, hw_pitch,
CURSOR_LINES_PER_CHUNK, lpc);
dcn10_cursor_program_control(ippn10,
attr->attribute_flags.bits.INVERT_PIXEL_DATA,
attr->color_format);
}
static void dcn10_cursor_set_position(
struct input_pixel_processor *ipp,
const struct dc_cursor_position *pos,
const struct dc_cursor_mi_param *param)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
uint32_t cur_en = pos->enable ? 1 : 0;
uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
dst_x_offset *= param->ref_clk_khz;
dst_x_offset /= param->pixel_clk_khz;
ASSERT(param->h_scale_ratio.value);
if (param->h_scale_ratio.value)
dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div(
dal_fixed31_32_from_int(dst_x_offset),
param->h_scale_ratio));
if (src_x_offset >= (int)param->viewport_width)
cur_en = 0; /* not visible beyond right edge*/
if (src_x_offset + (int)ippn10->curs_attr.width < 0)
cur_en = 0; /* not visible beyond left edge*/
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
dcn10_cursor_set_attributes(ipp, &ippn10->curs_attr);
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, cur_en);
REG_UPDATE(CURSOR0_CONTROL,
CUR0_ENABLE, cur_en);
REG_SET_2(CURSOR_POSITION, 0,
CURSOR_X_POSITION, pos->x,
CURSOR_Y_POSITION, pos->y);
REG_SET_2(CURSOR_HOT_SPOT, 0,
CURSOR_HOT_SPOT_X, pos->x_hotspot,
CURSOR_HOT_SPOT_Y, pos->y_hotspot);
REG_SET(CURSOR_DST_OFFSET, 0,
CURSOR_DST_X_OFFSET, dst_x_offset);
/* TODO Handle surface pixel formats other than 4:4:4 */
}
enum pixel_format_description {
PIXEL_FORMAT_FIXED = 0,
PIXEL_FORMAT_FIXED16,
PIXEL_FORMAT_FLOAT
};
static void dcn10_setup_format_flags(enum surface_pixel_format input_format,\
enum pixel_format_description *fmt)
{
if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
*fmt = PIXEL_FORMAT_FLOAT;
else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
*fmt = PIXEL_FORMAT_FIXED16;
else
*fmt = PIXEL_FORMAT_FIXED;
}
static void dcn10_ipp_set_degamma_format_float(struct input_pixel_processor *ipp,
bool is_float)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
if (is_float) {
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
} else {
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
}
}
static void dcn10_ipp_cnv_setup (
struct input_pixel_processor *ipp,
enum surface_pixel_format input_format,
enum expansion_mode mode,
enum ipp_output_format cnv_out_format)
{
uint32_t pixel_format;
uint32_t alpha_en;
enum pixel_format_description fmt ;
enum dc_color_space color_space;
enum dcn10_input_csc_select select;
bool is_float;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
bool force_disable_cursor = false;
dcn10_setup_format_flags(input_format, &fmt);
alpha_en = 1;
pixel_format = 0;
color_space = COLOR_SPACE_SRGB;
select = INPUT_CSC_SELECT_BYPASS;
is_float = false;
switch (fmt) {
case PIXEL_FORMAT_FIXED:
case PIXEL_FORMAT_FIXED16:
/*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
REG_SET_3(FORMAT_CONTROL, 0,
CNVC_BYPASS, 0,
FORMAT_EXPANSION_MODE, mode,
OUTPUT_FP, 0);
break;
case PIXEL_FORMAT_FLOAT:
REG_SET_3(FORMAT_CONTROL, 0,
CNVC_BYPASS, 0,
FORMAT_EXPANSION_MODE, mode,
OUTPUT_FP, 1);
is_float = true;
break;
default:
break;
}
dcn10_ipp_set_degamma_format_float(ipp, is_float);
switch (input_format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
pixel_format = 1;
break;
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
pixel_format = 3;
alpha_en = 0;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
pixel_format = 8;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
pixel_format = 10;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
force_disable_cursor = false;
pixel_format = 65;
color_space = COLOR_SPACE_YCBCR709;
select = INPUT_CSC_SELECT_ICSC;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
force_disable_cursor = true;
pixel_format = 64;
color_space = COLOR_SPACE_YCBCR709;
select = INPUT_CSC_SELECT_ICSC;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
force_disable_cursor = true;
pixel_format = 67;
color_space = COLOR_SPACE_YCBCR709;
select = INPUT_CSC_SELECT_ICSC;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
force_disable_cursor = true;
pixel_format = 66;
color_space = COLOR_SPACE_YCBCR709;
select = INPUT_CSC_SELECT_ICSC;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
pixel_format = 22;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
pixel_format = 24;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
pixel_format = 25;
break;
default:
break;
}
REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
REG_UPDATE(FORMAT_CONTROL, ALPHA_EN, alpha_en);
dcn10_program_input_csc(ipp, color_space, select);
if (force_disable_cursor) {
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, 0);
REG_UPDATE(CURSOR0_CONTROL,
CUR0_ENABLE, 0);
}
}
static bool dcn10_degamma_ram_inuse(struct input_pixel_processor *ipp,
bool *ram_a_inuse)
{
bool ret = false;
uint32_t status_reg = 0;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
status_reg = (REG_READ(CM_IGAM_LUT_RW_CONTROL) & 0x0F00) >>16;
if (status_reg == 9) {
*ram_a_inuse = true;
ret = true;
} else if (status_reg == 10) {
*ram_a_inuse = false;
ret = true;
}
return ret;
}
static void dcn10_degamma_ram_select(struct input_pixel_processor *ipp,
bool use_ram_a)
{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
if (use_ram_a)
REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
else
REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
}
static void dcn10_ipp_set_degamma_pwl(struct input_pixel_processor *ipp,
const struct pwl_params *params)
{
bool is_ram_a = true;
ipp_power_on_degamma_lut(ipp, true);
dcn10_ipp_enable_cm_block(ipp);
dcn10_degamma_ram_inuse(ipp, &is_ram_a);
if (is_ram_a == true)
dcn10_ipp_program_degamma_lutb_settings(ipp, params);
else
dcn10_ipp_program_degamma_luta_settings(ipp, params);
ipp_program_degamma_lut(ipp, params->rgb_resulted,
params->hw_points_num, !is_ram_a);
dcn10_degamma_ram_select(ipp, !is_ram_a);
}
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
static void dcn10_ipp_destroy(struct input_pixel_processor **ipp)
{
dm_free(TO_DCN10_IPP(*ipp));
*ipp = NULL;
}
static const struct ipp_funcs dcn10_ipp_funcs = {
.ipp_cursor_set_attributes = dcn10_cursor_set_attributes,
.ipp_cursor_set_position = dcn10_cursor_set_position,
.ipp_set_degamma = dcn10_ipp_set_degamma,
.ipp_full_bypass = dcn10_ipp_full_bypass,
.ipp_setup = dcn10_ipp_cnv_setup,
.ipp_program_degamma_pwl = dcn10_ipp_set_degamma_pwl,
.ipp_destroy = dcn10_ipp_destroy
};
void dcn10_ipp_construct(
struct dcn10_ipp *ippn10,
struct dc_context *ctx,
int inst,
const struct dcn10_ipp_registers *regs,
const struct dcn10_ipp_shift *ipp_shift,
const struct dcn10_ipp_mask *ipp_mask)
{
ippn10->base.ctx = ctx;
ippn10->base.inst = inst;
ippn10->base.funcs = &dcn10_ipp_funcs;
ippn10->regs = regs;
ippn10->ipp_shift = ipp_shift;
ippn10->ipp_mask = ipp_mask;
}

549
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h Normal file
View File

@ -0,0 +1,549 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCN10_IPP_H_
#define _DCN10_IPP_H_
#include "ipp.h"
#define TO_DCN10_IPP(ipp)\
container_of(ipp, struct dcn10_ipp, base)
#define IPP_DCN10_REG_LIST(id) \
SRI(CM_ICSC_CONTROL, CM, id), \
SRI(CM_ICSC_C11_C12, CM, id), \
SRI(CM_ICSC_C13_C14, CM, id), \
SRI(CM_ICSC_C21_C22, CM, id), \
SRI(CM_ICSC_C23_C24, CM, id), \
SRI(CM_ICSC_C31_C32, CM, id), \
SRI(CM_ICSC_C33_C34, CM, id), \
SRI(CM_COMA_C11_C12, CM, id), \
SRI(CM_COMA_C13_C14, CM, id), \
SRI(CM_COMA_C21_C22, CM, id), \
SRI(CM_COMA_C23_C24, CM, id), \
SRI(CM_COMA_C31_C32, CM, id), \
SRI(CM_COMA_C33_C34, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
SRI(CM_DGAM_RAMB_REGION_2_3, CM, id), \
SRI(CM_DGAM_RAMB_REGION_4_5, CM, id), \
SRI(CM_DGAM_RAMB_REGION_6_7, CM, id), \
SRI(CM_DGAM_RAMB_REGION_8_9, CM, id), \
SRI(CM_DGAM_RAMB_REGION_10_11, CM, id), \
SRI(CM_DGAM_RAMB_REGION_12_13, CM, id), \
SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
SRI(CM_DGAM_RAMA_REGION_2_3, CM, id), \
SRI(CM_DGAM_RAMA_REGION_4_5, CM, id), \
SRI(CM_DGAM_RAMA_REGION_6_7, CM, id), \
SRI(CM_DGAM_RAMA_REGION_8_9, CM, id), \
SRI(CM_DGAM_RAMA_REGION_10_11, CM, id), \
SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
SRI(CM_IGAM_CONTROL, CM, id), \
SRI(DPP_CONTROL, DPP_TOP, id), \
SRI(CURSOR_SETTINS, HUBPREQ, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
SRI(CURSOR_SIZE, CURSOR, id), \
SRI(CURSOR_CONTROL, CURSOR, id), \
SRI(CURSOR_POSITION, CURSOR, id), \
SRI(CURSOR_HOT_SPOT, CURSOR, id), \
SRI(CURSOR_DST_OFFSET, CURSOR, id)
#define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define IPP_DCN10_MASK_SH_LIST(mask_sh) \
IPP_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C13, mask_sh), \
IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C14, mask_sh), \
IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C21, mask_sh), \
IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C22, mask_sh), \
IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C23, mask_sh), \
IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C24, mask_sh), \
IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C31, mask_sh), \
IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \
IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \
IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \
IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \
IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh), \
IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh), \
IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh), \
IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh), \
IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh), \
IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh), \
IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh), \
IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh), \
IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
IPP_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_INVERT_MODE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MAX, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MIN, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
#define IPP_DCN10_REG_FIELD_LIST(type) \
type CM_ICSC_MODE; \
type CM_ICSC_C11; \
type CM_ICSC_C12; \
type CM_ICSC_C13; \
type CM_ICSC_C14; \
type CM_ICSC_C21; \
type CM_ICSC_C22; \
type CM_ICSC_C23; \
type CM_ICSC_C24; \
type CM_ICSC_C31; \
type CM_ICSC_C32; \
type CM_ICSC_C33; \
type CM_ICSC_C34; \
type CM_COMA_C11; \
type CM_COMA_C12; \
type CM_COMA_C13; \
type CM_COMA_C14; \
type CM_COMA_C21; \
type CM_COMA_C22; \
type CM_COMA_C23; \
type CM_COMA_C24; \
type CM_COMA_C31; \
type CM_COMA_C32; \
type CM_COMA_C33; \
type CM_COMA_C34; \
type CM_DGAM_RAMB_EXP_REGION_START_B; \
type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
type CM_DGAM_RAMB_EXP_REGION_START_G; \
type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
type CM_DGAM_RAMB_EXP_REGION_START_R; \
type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
type CM_DGAM_RAMB_EXP_REGION_END_B; \
type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
type CM_DGAM_RAMB_EXP_REGION_END_G; \
type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
type CM_DGAM_RAMB_EXP_REGION_END_R; \
type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION_START_B; \
type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
type CM_DGAM_RAMA_EXP_REGION_START_G; \
type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
type CM_DGAM_RAMA_EXP_REGION_START_R; \
type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
type CM_DGAM_RAMA_EXP_REGION_END_B; \
type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
type CM_DGAM_RAMA_EXP_REGION_END_G; \
type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
type CM_DGAM_RAMA_EXP_REGION_END_R; \
type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
type SHARED_MEM_PWR_DIS; \
type CM_IGAM_LUT_HOST_EN; \
type CM_DGAM_LUT_WRITE_EN_MASK; \
type CM_DGAM_LUT_WRITE_SEL; \
type CM_DGAM_LUT_INDEX; \
type CM_DGAM_LUT_DATA; \
type DPP_CLOCK_ENABLE; \
type CM_BYPASS_EN; \
type CNVC_SURFACE_PIXEL_FORMAT; \
type CNVC_BYPASS; \
type ALPHA_EN; \
type FORMAT_EXPANSION_MODE; \
type CM_DGAM_LUT_MODE; \
type CM_IGAM_LUT_MODE; \
type CURSOR0_DST_Y_OFFSET; \
type CURSOR0_CHUNK_HDL_ADJUST; \
type CUR0_MODE; \
type CUR0_INVERT_MODE; \
type CUR0_COLOR0; \
type CUR0_COLOR1; \
type CUR0_EXPANSION_MODE; \
type CUR0_MAX; \
type CUR0_MIN; \
type CURSOR_SURFACE_ADDRESS_HIGH; \
type CURSOR_SURFACE_ADDRESS; \
type CURSOR_WIDTH; \
type CURSOR_HEIGHT; \
type CURSOR_MODE; \
type CURSOR_PITCH; \
type CURSOR_LINES_PER_CHUNK; \
type CURSOR_ENABLE; \
type CUR0_ENABLE; \
type CURSOR_X_POSITION; \
type CURSOR_Y_POSITION; \
type CURSOR_HOT_SPOT_X; \
type CURSOR_HOT_SPOT_Y; \
type CURSOR_DST_X_OFFSET; \
type CM_IGAM_INPUT_FORMAT; \
type OUTPUT_FP
struct dcn10_ipp_shift {
IPP_DCN10_REG_FIELD_LIST(uint8_t);
};
struct dcn10_ipp_mask {
IPP_DCN10_REG_FIELD_LIST(uint32_t);
};
struct dcn10_ipp_registers {
uint32_t CM_ICSC_CONTROL;
uint32_t CM_ICSC_C11_C12;
uint32_t CM_ICSC_C13_C14;
uint32_t CM_ICSC_C21_C22;
uint32_t CM_ICSC_C23_C24;
uint32_t CM_ICSC_C31_C32;
uint32_t CM_ICSC_C33_C34;
uint32_t CM_COMA_C11_C12;
uint32_t CM_COMA_C13_C14;
uint32_t CM_COMA_C21_C22;
uint32_t CM_COMA_C23_C24;
uint32_t CM_COMA_C31_C32;
uint32_t CM_COMA_C33_C34;
uint32_t CM_DGAM_RAMB_START_CNTL_B;
uint32_t CM_DGAM_RAMB_START_CNTL_G;
uint32_t CM_DGAM_RAMB_START_CNTL_R;
uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B;
uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G;
uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R;
uint32_t CM_DGAM_RAMB_END_CNTL1_B;
uint32_t CM_DGAM_RAMB_END_CNTL2_B;
uint32_t CM_DGAM_RAMB_END_CNTL1_G;
uint32_t CM_DGAM_RAMB_END_CNTL2_G;
uint32_t CM_DGAM_RAMB_END_CNTL1_R;
uint32_t CM_DGAM_RAMB_END_CNTL2_R;
uint32_t CM_DGAM_RAMB_REGION_0_1;
uint32_t CM_DGAM_RAMB_REGION_2_3;
uint32_t CM_DGAM_RAMB_REGION_4_5;
uint32_t CM_DGAM_RAMB_REGION_6_7;
uint32_t CM_DGAM_RAMB_REGION_8_9;
uint32_t CM_DGAM_RAMB_REGION_10_11;
uint32_t CM_DGAM_RAMB_REGION_12_13;
uint32_t CM_DGAM_RAMB_REGION_14_15;
uint32_t CM_DGAM_RAMA_START_CNTL_B;
uint32_t CM_DGAM_RAMA_START_CNTL_G;
uint32_t CM_DGAM_RAMA_START_CNTL_R;
uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B;
uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G;
uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R;
uint32_t CM_DGAM_RAMA_END_CNTL1_B;
uint32_t CM_DGAM_RAMA_END_CNTL2_B;
uint32_t CM_DGAM_RAMA_END_CNTL1_G;
uint32_t CM_DGAM_RAMA_END_CNTL2_G;
uint32_t CM_DGAM_RAMA_END_CNTL1_R;
uint32_t CM_DGAM_RAMA_END_CNTL2_R;
uint32_t CM_DGAM_RAMA_REGION_0_1;
uint32_t CM_DGAM_RAMA_REGION_2_3;
uint32_t CM_DGAM_RAMA_REGION_4_5;
uint32_t CM_DGAM_RAMA_REGION_6_7;
uint32_t CM_DGAM_RAMA_REGION_8_9;
uint32_t CM_DGAM_RAMA_REGION_10_11;
uint32_t CM_DGAM_RAMA_REGION_12_13;
uint32_t CM_DGAM_RAMA_REGION_14_15;
uint32_t CM_MEM_PWR_CTRL;
uint32_t CM_IGAM_LUT_RW_CONTROL;
uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
uint32_t CM_DGAM_LUT_INDEX;
uint32_t CM_DGAM_LUT_DATA;
uint32_t CM_CONTROL;
uint32_t CM_DGAM_CONTROL;
uint32_t CM_IGAM_CONTROL;
uint32_t DPP_CONTROL;
uint32_t CURSOR_SETTINS;
uint32_t CNVC_SURFACE_PIXEL_FORMAT;
uint32_t CURSOR0_CONTROL;
uint32_t CURSOR0_COLOR0;
uint32_t CURSOR0_COLOR1;
uint32_t FORMAT_CONTROL;
uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
uint32_t CURSOR_SURFACE_ADDRESS;
uint32_t CURSOR_SIZE;
uint32_t CURSOR_CONTROL;
uint32_t CURSOR_POSITION;
uint32_t CURSOR_HOT_SPOT;
uint32_t CURSOR_DST_OFFSET;
};
struct dcn10_ipp {
struct input_pixel_processor base;
const struct dcn10_ipp_registers *regs;
const struct dcn10_ipp_shift *ipp_shift;
const struct dcn10_ipp_mask *ipp_mask;
struct dc_cursor_attributes curs_attr;
};
void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
struct dc_context *ctx,
int inst,
const struct dcn10_ipp_registers *regs,
const struct dcn10_ipp_shift *ipp_shift,
const struct dcn10_ipp_mask *ipp_mask);
#endif /* _DCN10_IPP_H_ */

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c Normal file
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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h Normal file
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@ -0,0 +1,553 @@
/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_MEM_INPUT_DCN10_H__
#define __DC_MEM_INPUT_DCN10_H__
#include "mem_input.h"
#define TO_DCN10_MEM_INPUT(mi)\
container_of(mi, struct dcn10_mem_input, base)
#define MI_DCN10_REG_LIST(id)\
SRI(DCHUBP_CNTL, HUBP, id),\
SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
SRI(DCSURF_TILING_CONFIG, HUBP, id),\
SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
SRI(HUBPRET_CONTROL, HUBPRET, id),\
SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
SRI(BLANK_OFFSET_0, HUBPREQ, id),\
SRI(BLANK_OFFSET_1, HUBPREQ, id),\
SRI(DST_DIMENSIONS, HUBPREQ, id),\
SRI(DST_AFTER_SCALER, HUBPREQ, id),\
SRI(PREFETCH_SETTINS, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
SR(DCHUBBUB_SDPIF_FB_TOP),\
SR(DCHUBBUB_SDPIF_FB_BASE),\
SR(DCHUBBUB_SDPIF_FB_OFFSET),\
SR(DCHUBBUB_SDPIF_AGP_BASE),\
SR(DCHUBBUB_SDPIF_AGP_BOT),\
SR(DCHUBBUB_SDPIF_AGP_TOP),\
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
SR(DCHUBBUB_ARB_SAT_LEVEL),\
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
/* todo: get these from GVM instead of reading registers ourselves */\
GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
GC_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
GC_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
struct dcn_mi_registers {
uint32_t DCHUBP_CNTL;
uint32_t HUBPREQ_DEBUG_DB;
uint32_t DCSURF_ADDR_CONFIG;
uint32_t DCSURF_TILING_CONFIG;
uint32_t DCSURF_SURFACE_PITCH;
uint32_t DCSURF_SURFACE_PITCH_C;
uint32_t DCSURF_SURFACE_CONFIG;
uint32_t DCSURF_FLIP_CONTROL;
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
uint32_t DCSURF_SURFACE_CONTROL;
uint32_t HUBPRET_CONTROL;
uint32_t DCN_EXPANSION_MODE;
uint32_t DCHUBP_REQ_SIZE_CONFIG;
uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
uint32_t BLANK_OFFSET_0;
uint32_t BLANK_OFFSET_1;
uint32_t DST_DIMENSIONS;
uint32_t DST_AFTER_SCALER;
uint32_t PREFETCH_SETTINS;
uint32_t VBLANK_PARAMETERS_0;
uint32_t REF_FREQ_TO_PIX_FREQ;
uint32_t VBLANK_PARAMETERS_1;
uint32_t VBLANK_PARAMETERS_3;
uint32_t NOM_PARAMETERS_0;
uint32_t NOM_PARAMETERS_1;
uint32_t NOM_PARAMETERS_4;
uint32_t NOM_PARAMETERS_5;
uint32_t PER_LINE_DELIVERY_PRE;
uint32_t PER_LINE_DELIVERY;
uint32_t PREFETCH_SETTINS_C;
uint32_t VBLANK_PARAMETERS_2;
uint32_t VBLANK_PARAMETERS_4;
uint32_t NOM_PARAMETERS_2;
uint32_t NOM_PARAMETERS_3;
uint32_t NOM_PARAMETERS_6;
uint32_t NOM_PARAMETERS_7;
uint32_t DCN_TTU_QOS_WM;
uint32_t DCN_GLOBAL_TTU_CNTL;
uint32_t DCN_SURF0_TTU_CNTL0;
uint32_t DCN_SURF0_TTU_CNTL1;
uint32_t DCN_SURF1_TTU_CNTL0;
uint32_t DCN_SURF1_TTU_CNTL1;
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
uint32_t DCN_VM_MX_L1_TLB_CNTL;
uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
uint32_t DCHUBBUB_SDPIF_FB_TOP;
uint32_t DCHUBBUB_SDPIF_FB_BASE;
uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
uint32_t DCHUBBUB_SDPIF_AGP_BASE;
uint32_t DCHUBBUB_SDPIF_AGP_BOT;
uint32_t DCHUBBUB_SDPIF_AGP_TOP;
uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
uint32_t DCHUBBUB_ARB_SAT_LEVEL;
uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
/* GC registers. read only. temporary hack */
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
};
#define MI_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define MI_DCN10_MASK_SH_LIST(mask_sh)\
MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
MI_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh),\
MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
MI_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh),\
MI_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh),\
MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\
MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\
MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\
MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\
MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh),\
/* todo: get these from GVM instead of reading registers ourselves */\
MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
MI_SF(MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh)
#define DCN_MI_REG_FIELD_LIST(type) \
type HUBP_BLANK_EN;\
type HUBP_TTU_DISABLE;\
type NUM_PIPES;\
type NUM_BANKS;\
type PIPE_INTERLEAVE;\
type NUM_SE;\
type NUM_RB_PER_SE;\
type MAX_COMPRESSED_FRAGS;\
type SW_MODE;\
type META_LINEAR;\
type RB_ALIGNED;\
type PIPE_ALIGNED;\
type PITCH;\
type META_PITCH;\
type PITCH_C;\
type META_PITCH_C;\
type ROTATION_ANGLE;\
type H_MIRROR_EN;\
type SURFACE_PIXEL_FORMAT;\
type SURFACE_FLIP_TYPE;\
type SURFACE_UPDATE_PENDING;\
type PRIMARY_SURFACE_ADDRESS_HIGH;\
type PRIMARY_SURFACE_ADDRESS;\
type SECONDARY_SURFACE_ADDRESS_HIGH;\
type SECONDARY_SURFACE_ADDRESS;\
type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
type PRIMARY_META_SURFACE_ADDRESS;\
type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
type SECONDARY_META_SURFACE_ADDRESS;\
type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
type PRIMARY_SURFACE_ADDRESS_C;\
type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
type PRIMARY_META_SURFACE_ADDRESS_C;\
type PRIMARY_SURFACE_DCC_EN;\
type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
type DET_BUF_PLANE1_BASE_ADDRESS;\
type CROSSBAR_SRC_CB_B;\
type CROSSBAR_SRC_CR_R;\
type DRQ_EXPANSION_MODE;\
type PRQ_EXPANSION_MODE;\
type MRQ_EXPANSION_MODE;\
type CRQ_EXPANSION_MODE;\
type CHUNK_SIZE;\
type MIN_CHUNK_SIZE;\
type META_CHUNK_SIZE;\
type MIN_META_CHUNK_SIZE;\
type DPTE_GROUP_SIZE;\
type MPTE_GROUP_SIZE;\
type SWATH_HEIGHT;\
type PTE_ROW_HEIGHT_LINEAR;\
type CHUNK_SIZE_C;\
type MIN_CHUNK_SIZE_C;\
type META_CHUNK_SIZE_C;\
type MIN_META_CHUNK_SIZE_C;\
type DPTE_GROUP_SIZE_C;\
type MPTE_GROUP_SIZE_C;\
type SWATH_HEIGHT_C;\
type PTE_ROW_HEIGHT_LINEAR_C;\
type REFCYC_H_BLANK_END;\
type DLG_V_BLANK_END;\
type MIN_DST_Y_NEXT_START;\
type REFCYC_PER_HTOTAL;\
type REFCYC_X_AFTER_SCALER;\
type DST_Y_AFTER_SCALER;\
type DST_Y_PREFETCH;\
type VRATIO_PREFETCH;\
type DST_Y_PER_VM_VBLANK;\
type DST_Y_PER_ROW_VBLANK;\
type REF_FREQ_TO_PIX_FREQ;\
type REFCYC_PER_PTE_GROUP_VBLANK_L;\
type REFCYC_PER_META_CHUNK_VBLANK_L;\
type DST_Y_PER_PTE_ROW_NOM_L;\
type REFCYC_PER_PTE_GROUP_NOM_L;\
type DST_Y_PER_META_ROW_NOM_L;\
type REFCYC_PER_META_CHUNK_NOM_L;\
type REFCYC_PER_LINE_DELIVERY_PRE_L;\
type REFCYC_PER_LINE_DELIVERY_PRE_C;\
type REFCYC_PER_LINE_DELIVERY_L;\
type REFCYC_PER_LINE_DELIVERY_C;\
type VRATIO_PREFETCH_C;\
type REFCYC_PER_PTE_GROUP_VBLANK_C;\
type REFCYC_PER_META_CHUNK_VBLANK_C;\
type DST_Y_PER_PTE_ROW_NOM_C;\
type REFCYC_PER_PTE_GROUP_NOM_C;\
type DST_Y_PER_META_ROW_NOM_C;\
type REFCYC_PER_META_CHUNK_NOM_C;\
type QoS_LEVEL_LOW_WM;\
type QoS_LEVEL_HIGH_WM;\
type MIN_TTU_VBLANK;\
type QoS_LEVEL_FLIP;\
type REFCYC_PER_REQ_DELIVERY;\
type QoS_LEVEL_FIXED;\
type QoS_RAMP_DISABLE;\
type REFCYC_PER_REQ_DELIVERY_PRE;\
type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
type ENABLE_L1_TLB;\
type SYSTEM_ACCESS_MODE;\
type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
type SDPIF_FB_TOP;\
type SDPIF_FB_BASE;\
type SDPIF_FB_OFFSET;\
type SDPIF_AGP_BASE;\
type SDPIF_AGP_BOT;\
type SDPIF_AGP_TOP;\
type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
type DCHUBBUB_ARB_SAT_LEVEL;\
type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
/* todo: get these from GVM instead of reading registers ourselves */\
type PAGE_DIRECTORY_ENTRY_HI32;\
type PAGE_DIRECTORY_ENTRY_LO32;\
type LOGICAL_PAGE_NUMBER_HI4;\
type LOGICAL_PAGE_NUMBER_LO32;\
type PHYSICAL_PAGE_ADDR_HI4;\
type PHYSICAL_PAGE_ADDR_LO32;\
type PHYSICAL_PAGE_NUMBER_MSB;\
type PHYSICAL_PAGE_NUMBER_LSB;\
type LOGICAL_ADDR
struct dcn_mi_shift {
DCN_MI_REG_FIELD_LIST(uint8_t);
};
struct dcn_mi_mask {
DCN_MI_REG_FIELD_LIST(uint32_t);
};
struct dcn10_mem_input {
struct mem_input base;
const struct dcn_mi_registers *mi_regs;
const struct dcn_mi_shift *mi_shift;
const struct dcn_mi_mask *mi_mask;
};
bool dcn10_mem_input_construct(
struct dcn10_mem_input *mi,
struct dc_context *ctx,
uint32_t inst,
const struct dcn_mi_registers *mi_regs,
const struct dcn_mi_shift *mi_shift,
const struct dcn_mi_mask *mi_mask);
#endif

376
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c Normal file
View File

@ -0,0 +1,376 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "reg_helper.h"
#include "dcn10_mpc.h"
#define REG(reg)\
mpc->mpc_regs->reg
#define CTX \
mpc->base.ctx
#undef FN
#define FN(reg_name, field_name) \
mpc->mpc_shift->field_name, mpc->mpc_mask->field_name
/* Internal function to set mpc output mux */
static void set_output_mux(struct dcn10_mpc *mpc,
uint8_t opp_id,
uint8_t mpcc_id)
{
if (mpcc_id != 0xf)
REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
OPP_PIPE_CLOCK_EN, 1);
REG_SET(MUX[opp_id], 0,
MPC_OUT_MUX, mpcc_id);
/* TODO: Move to post when ready.
if (mpcc_id == 0xf) {
MPCC_REG_UPDATE(OPP_PIPE0_OPP_PIPE_CONTROL,
OPP_PIPE_CLOCK_EN, 0);
}
*/
}
static void set_blend_mode(struct dcn10_mpc *mpc,
enum blend_mode mode,
uint8_t mpcc_id)
{
/* Enable per-pixel alpha on this pipe */
if (mode == TOP_BLND)
REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
MPCC_ALPHA_BLND_MODE, 0,
MPCC_ALPHA_MULTIPLIED_MODE, 0,
MPCC_BLND_ACTIVE_OVERLAP_ONLY, 0);
else
REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
MPCC_ALPHA_BLND_MODE, 0,
MPCC_ALPHA_MULTIPLIED_MODE, 1,
MPCC_BLND_ACTIVE_OVERLAP_ONLY, 1);
}
void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc,
unsigned int mpcc_inst,
struct tg_color *bg_color)
{
/* mpc color is 12 bit. tg_color is 10 bit */
/* todo: might want to use 16 bit to represent color and have each
* hw block translate to correct color depth.
*/
uint32_t bg_r_cr = bg_color->color_r_cr << 2;
uint32_t bg_g_y = bg_color->color_g_y << 2;
uint32_t bg_b_cb = bg_color->color_b_cb << 2;
REG_SET(MPCC_BG_R_CR[mpcc_inst], 0,
MPCC_BG_R_CR, bg_r_cr);
REG_SET(MPCC_BG_G_Y[mpcc_inst], 0,
MPCC_BG_G_Y, bg_g_y);
REG_SET(MPCC_BG_B_CB[mpcc_inst], 0,
MPCC_BG_B_CB, bg_b_cb);
}
/* This function programs MPC tree configuration
* Assume it is the initial time to setup MPC tree_configure, means
* the instance of dpp/mpcc/opp specified in structure tree_cfg are
* in idle status.
* Before invoke this function, ensure that master lock of OPTC specified
* by opp_id is set.
*
* tree_cfg[in] - new MPC_TREE_CFG
*/
void dcn10_set_mpc_tree(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg)
{
int i;
for (i = 0; i < tree_cfg->num_pipes; i++) {
uint8_t mpcc_inst = tree_cfg->mpcc[i];
REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
MPCC_OPP_ID, tree_cfg->opp_id);
REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
MPCC_TOP_SEL, tree_cfg->dpp[i]);
if (i == tree_cfg->num_pipes-1) {
REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
MPCC_BOT_SEL, 0xF);
/* MPCC_CONTROL->MPCC_MODE */
REG_UPDATE(MPCC_CONTROL[mpcc_inst],
MPCC_MODE, tree_cfg->mode);
} else {
REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
MPCC_BOT_SEL, tree_cfg->dpp[i+1]);
/* MPCC_CONTROL->MPCC_MODE */
REG_UPDATE(MPCC_CONTROL[mpcc_inst],
MPCC_MODE, 3);
}
if (i == 0)
set_output_mux(
mpc, tree_cfg->opp_id, mpcc_inst);
set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
}
}
void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
uint8_t dpp_idx,
uint8_t mpcc_idx,
uint8_t opp_idx)
{
struct mpc_tree_cfg tree_cfg = { 0 };
tree_cfg.num_pipes = 1;
tree_cfg.opp_id = opp_idx;
tree_cfg.mode = TOP_PASSTHRU;
/* TODO: FPGA bring up one MPC has only 1 DPP and 1 MPCC
* For blend case, need fill mode DPP and cascade MPCC
*/
tree_cfg.dpp[0] = dpp_idx;
tree_cfg.mpcc[0] = mpcc_idx;
dcn10_set_mpc_tree(mpc, &tree_cfg);
}
/*
* This is the function to remove current MPC tree specified by tree_cfg
* Before invoke this function, ensure that master lock of OPTC specified
* by opp_id is set.
*
*tree_cfg[in/out] - current MPC_TREE_CFG
*/
void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg)
{
int i;
for (i = 0; i < tree_cfg->num_pipes; i++) {
uint8_t mpcc_inst = tree_cfg->mpcc[i];
REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
MPCC_OPP_ID, 0xf);
REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
MPCC_TOP_SEL, 0xf);
REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
MPCC_BOT_SEL, 0xF);
/* add remove dpp/mpcc pair into pending list
* TODO FPGA AddToPendingList if empty from pseudo code
*/
tree_cfg->dpp[i] = 0xf;
tree_cfg->mpcc[i] = 0xf;
}
set_output_mux(mpc, tree_cfg->opp_id, 0xf);
tree_cfg->opp_id = 0xf;
tree_cfg->num_pipes = 0;
}
/* TODO FPGA: how to handle DPP?
* Function to remove one of pipe from MPC configure tree by dpp idx
* Before invoke this function, ensure that master lock of OPTC specified
* by opp_id is set
* This function can be invoke multiple times to remove more than 1 dpps.
*
* tree_cfg[in/out] - current MPC_TREE_CFG
* idx[in] - index of dpp from tree_cfg to be removed.
*/
bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg,
uint8_t idx)
{
int i;
bool found = false;
/* find dpp_idx from dpp array of tree_cfg */
for (i = 0; i < tree_cfg->num_pipes; i++) {
if (tree_cfg->dpp[i] == idx) {
found = true;
break;
}
}
if (found) {
/* add remove dpp/mpcc pair into pending list */
/* TODO FPGA AddToPendingList if empty from pseudo code
* AddToPendingList(tree_cfg->dpp[i],tree_cfg->mpcc[i]);
*/
uint8_t mpcc_inst = tree_cfg->mpcc[i];
REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
MPCC_OPP_ID, 0xf);
REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
MPCC_TOP_SEL, 0xf);
REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
MPCC_BOT_SEL, 0xF);
if (i == 0) {
if (tree_cfg->num_pipes > 1)
set_output_mux(mpc,
tree_cfg->opp_id, tree_cfg->mpcc[i+1]);
else
set_output_mux(mpc, tree_cfg->opp_id, 0xf);
} else if (i == tree_cfg->num_pipes-1) {
mpcc_inst = tree_cfg->mpcc[i - 1];
REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
MPCC_BOT_SEL, 0xF);
REG_UPDATE(MPCC_CONTROL[mpcc_inst],
MPCC_MODE, tree_cfg->mode);
} else {
mpcc_inst = tree_cfg->mpcc[i - 1];
REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
MPCC_BOT_SEL, tree_cfg->mpcc[i+1]);
}
set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
/* update tree_cfg structure */
while (i < tree_cfg->num_pipes - 1) {
tree_cfg->dpp[i] = tree_cfg->dpp[i+1];
tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1];
i++;
}
tree_cfg->num_pipes--;
}
return found;
}
/* TODO FPGA: how to handle DPP?
* Function to add DPP/MPCC pair into MPC configure tree by position.
* Before invoke this function, ensure that master lock of OPTC specified
* by opp_id is set
* This function can be invoke multiple times to add more than 1 pipes.
*
* tree_cfg[in/out] - current MPC_TREE_CFG
* dpp_idx[in] - index of an idle dpp insatnce to be added.
* mpcc_idx[in] - index of an idle mpcc instance to be added.
* poistion[in] - position of dpp/mpcc pair to be added into current tree_cfg
* 0 means insert to the most top layer of MPC tree
*/
void dcn10_add_dpp(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg,
uint8_t dpp_idx,
uint8_t mpcc_idx,
uint8_t position)
{
uint8_t temp;
uint8_t temp1;
REG_SET(MPCC_OPP_ID[mpcc_idx], 0,
MPCC_OPP_ID, tree_cfg->opp_id);
REG_SET(MPCC_TOP_SEL[mpcc_idx], 0,
MPCC_TOP_SEL, dpp_idx);
if (position == 0) {
/* idle dpp/mpcc is added to the top layer of tree */
REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
MPCC_BOT_SEL, tree_cfg->mpcc[0]);
REG_UPDATE(MPCC_CONTROL[mpcc_idx],
MPCC_MODE, 3);
/* opp will get new output. from new added mpcc */
set_output_mux(mpc, tree_cfg->opp_id, mpcc_idx);
set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
} else if (position == tree_cfg->num_pipes) {
/* idle dpp/mpcc is added to the bottom layer of tree */
/* get instance of previous bottom mpcc, set to middle layer */
temp = tree_cfg->mpcc[tree_cfg->num_pipes - 1];
REG_SET(MPCC_BOT_SEL[temp], 0,
MPCC_BOT_SEL, mpcc_idx);
REG_UPDATE(MPCC_CONTROL[temp],
MPCC_MODE, 3);
/* mpcc_idx become new bottom mpcc*/
REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
MPCC_BOT_SEL, 0xf);
REG_UPDATE(MPCC_CONTROL[mpcc_idx],
MPCC_MODE, tree_cfg->mode);
set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
} else {
/* idle dpp/mpcc is added to middle of tree */
temp = tree_cfg->mpcc[position - 1];
temp1 = tree_cfg->mpcc[position];
/* new mpcc instance temp1 is added right after temp*/
REG_SET(MPCC_BOT_SEL[temp], 0,
MPCC_BOT_SEL, mpcc_idx);
/* mpcc_idx connect previous temp+1 to new mpcc */
REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
MPCC_BOT_SEL, temp1);
/* temp TODO: may not need*/
REG_UPDATE(MPCC_CONTROL[temp],
MPCC_MODE, 3);
set_blend_mode(mpc, tree_cfg->mode, temp);
}
/* update tree_cfg structure */
temp = tree_cfg->num_pipes - 1;
/*
* iterating from the last mpc/dpp pair to the one being added, shift
* them down one position
*/
while (temp > position) {
tree_cfg->dpp[temp + 1] = tree_cfg->dpp[temp];
tree_cfg->mpcc[temp + 1] = tree_cfg->mpcc[temp];
temp--;
}
/* insert the new mpc/dpp pair into the tree_cfg*/
tree_cfg->dpp[position] = dpp_idx;
tree_cfg->mpcc[position] = mpcc_idx;
tree_cfg->num_pipes++;
}
void wait_mpcc_idle(struct dcn10_mpc *mpc,
uint8_t mpcc_id)
{
REG_WAIT(MPCC_STATUS[mpcc_id],
MPCC_IDLE, 1,
1000, 1000);
}

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/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_MPC_DCN10_H__
#define __DC_MPC_DCN10_H__
#include "mpc.h"
#define TO_DCN10_MPC(mpc_base)\
container_of(mpc_base, struct dcn10_mpc, base)
#define MAX_MPCC 4
#define MAX_MPC_OUT 4
#define MAX_OPP 4
#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
SRII(MPCC_TOP_SEL, MPCC, inst),\
SRII(MPCC_BOT_SEL, MPCC, inst),\
SRII(MPCC_CONTROL, MPCC, inst),\
SRII(MPCC_STATUS, MPCC, inst),\
SRII(MPCC_OPP_ID, MPCC, inst),\
SRII(MPCC_BG_G_Y, MPCC, inst),\
SRII(MPCC_BG_R_CR, MPCC, inst),\
SRII(MPCC_BG_B_CB, MPCC, inst),\
SRII(MPCC_BG_B_CB, MPCC, inst),\
SRII(MUX, MPC_OUT, inst),\
SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst)
struct dcn_mpc_registers {
uint32_t MPCC_TOP_SEL[MAX_MPCC];
uint32_t MPCC_BOT_SEL[MAX_MPCC];
uint32_t MPCC_CONTROL[MAX_MPCC];
uint32_t MPCC_STATUS[MAX_MPCC];
uint32_t MPCC_OPP_ID[MAX_MPCC];
uint32_t MPCC_BG_G_Y[MAX_MPCC];
uint32_t MPCC_BG_R_CR[MAX_MPCC];
uint32_t MPCC_BG_B_CB[MAX_MPCC];
uint32_t MUX[MAX_MPC_OUT];
uint32_t OPP_PIPE_CONTROL[MAX_OPP];
};
#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh)
#define MPC_REG_FIELD_LIST(type) \
type MPCC_TOP_SEL;\
type MPCC_BOT_SEL;\
type MPCC_MODE;\
type MPCC_ALPHA_BLND_MODE;\
type MPCC_ALPHA_MULTIPLIED_MODE;\
type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
type MPCC_IDLE;\
type MPCC_OPP_ID;\
type MPCC_BG_G_Y;\
type MPCC_BG_R_CR;\
type MPCC_BG_B_CB;\
type MPC_OUT_MUX;\
type OPP_PIPE_CLOCK_EN;\
struct dcn_mpc_shift {
MPC_REG_FIELD_LIST(uint8_t)
};
struct dcn_mpc_mask {
MPC_REG_FIELD_LIST(uint32_t)
};
struct dcn10_mpc {
struct mpc base;
const struct dcn_mpc_registers *mpc_regs;
const struct dcn_mpc_shift *mpc_shift;
const struct dcn_mpc_mask *mpc_mask;
};
void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
uint8_t dpp_idx,
uint8_t mpcc_idx,
uint8_t opp_idx);
void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg);
bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg,
uint8_t idx);
void dcn10_add_dpp(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg,
uint8_t dpp_idx,
uint8_t mpcc_idx,
uint8_t position);
void wait_mpcc_idle(struct dcn10_mpc *mpc,
uint8_t mpcc_id);
void dcn10_set_mpc_tree(struct dcn10_mpc *mpc,
struct mpc_tree_cfg *tree_cfg);
void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc,
unsigned int mpcc_inst,
struct tg_color *bg_color);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dcn10_opp.h"
#include "reg_helper.h"
#define REG(reg) \
(oppn10->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
#define CTX \
oppn10->base.ctx
static void opp_set_regamma_mode(
struct output_pixel_processor *opp,
enum opp_regamma mode)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
uint32_t re_mode = 0;
uint32_t obuf_bypass = 0; /* need for pipe split */
uint32_t obuf_hupscale = 0;
switch (mode) {
case OPP_REGAMMA_BYPASS:
re_mode = 0;
break;
case OPP_REGAMMA_SRGB:
re_mode = 1;
break;
case OPP_REGAMMA_3_6:
re_mode = 2;
break;
case OPP_REGAMMA_USER:
re_mode = oppn10->is_write_to_ram_a_safe ? 3 : 4;
oppn10->is_write_to_ram_a_safe = !oppn10->is_write_to_ram_a_safe;
break;
default:
break;
}
REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
REG_UPDATE_2(OBUF_CONTROL,
OBUF_BYPASS, obuf_bypass,
OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
}
/************* FORMATTER ************/
/**
* set_truncation
* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
* 2) enable truncation
* 3) HW remove 12bit FMT support for DCE11 power saving reason.
*/
static void set_truncation(
struct dcn10_opp *oppn10,
const struct bit_depth_reduction_params *params)
{
REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED,
FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH,
FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
}
static void set_spatial_dither(
struct dcn10_opp *oppn10,
const struct bit_depth_reduction_params *params)
{
/*Disable spatial (random) dithering*/
REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
FMT_SPATIAL_DITHER_EN, 0,
FMT_SPATIAL_DITHER_MODE, 0,
FMT_SPATIAL_DITHER_DEPTH, 0,
FMT_TEMPORAL_DITHER_EN, 0,
FMT_HIGHPASS_RANDOM_ENABLE, 0,
FMT_FRAME_RANDOM_ENABLE, 0,
FMT_RGB_RANDOM_ENABLE, 0);
/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
if (params->flags.FRAME_RANDOM == 1) {
if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) {
REG_UPDATE_2(FMT_CONTROL,
FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
} else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
REG_UPDATE_2(FMT_CONTROL,
FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
} else {
return;
}
} else {
REG_UPDATE_2(FMT_CONTROL,
FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
}
/*Set seed for random values for
* spatial dithering for R,G,B channels*/
REG_SET(FMT_DITHER_RAND_R_SEED, 0,
FMT_RAND_R_SEED, params->r_seed_value);
REG_SET(FMT_DITHER_RAND_G_SEED, 0,
FMT_RAND_G_SEED, params->g_seed_value);
REG_SET(FMT_DITHER_RAND_B_SEED, 0,
FMT_RAND_B_SEED, params->b_seed_value);
/* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero
* offset for the R/Cr channel, lower 4LSB
* is forced to zeros. Typically set to 0
* RGB and 0x80000 YCbCr.
*/
/* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero
* offset for the G/Y channel, lower 4LSB is
* forced to zeros. Typically set to 0 RGB
* and 0x80000 YCbCr.
*/
/* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero
* offset for the B/Cb channel, lower 4LSB is
* forced to zeros. Typically set to 0 RGB and
* 0x80000 YCbCr.
*/
REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
/*Enable spatial dithering*/
FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED,
/* Set spatial dithering mode
* (default is Seed patterrn AAAA...)
*/
FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
/*Set spatial dithering bit depth*/
FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
/*Disable High pass filter*/
FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
/*Reset only at startup*/
FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
/*Set RGB data dithered with x^28+x^3+1*/
FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
}
static void opp_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
set_truncation(oppn10, params);
set_spatial_dither(oppn10, params);
/* TODO
* set_temporal_dither(oppn10, params);
*/
}
/**
* set_pixel_encoding
*
* Set Pixel Encoding
* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
* 1: YCbCr 4:2:2
*/
static void set_pixel_encoding(
struct dcn10_opp *oppn10,
const struct clamping_and_pixel_encoding_params *params)
{
switch (params->pixel_encoding) {
case PIXEL_ENCODING_RGB:
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
break;
case PIXEL_ENCODING_YCBCR422:
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
break;
case PIXEL_ENCODING_YCBCR420:
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
break;
default:
break;
}
}
/**
* Set Clamping
* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
* 1 for 8 bpc
* 2 for 10 bpc
* 3 for 12 bpc
* 7 for programable
* 2) Enable clamp if Limited range requested
*/
static void opp_set_clamping(
struct dcn10_opp *oppn10,
const struct clamping_and_pixel_encoding_params *params)
{
REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_DATA_EN, 0,
FMT_CLAMP_COLOR_FORMAT, 0);
switch (params->clamping_level) {
case CLAMPING_FULL_RANGE:
REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_DATA_EN, 1,
FMT_CLAMP_COLOR_FORMAT, 0);
break;
case CLAMPING_LIMITED_RANGE_8BPC:
REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_DATA_EN, 1,
FMT_CLAMP_COLOR_FORMAT, 1);
break;
case CLAMPING_LIMITED_RANGE_10BPC:
REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_DATA_EN, 1,
FMT_CLAMP_COLOR_FORMAT, 2);
break;
case CLAMPING_LIMITED_RANGE_12BPC:
REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_DATA_EN, 1,
FMT_CLAMP_COLOR_FORMAT, 3);
break;
case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
/* TODO */
default:
break;
}
}
static void opp_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
enum signal_type signal)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
FMT_DYNAMIC_EXP_EN, 0,
FMT_DYNAMIC_EXP_MODE, 0);
/*00 - 10-bit -> 12-bit dynamic expansion*/
/*01 - 8-bit -> 12-bit dynamic expansion*/
if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
switch (color_dpth) {
case COLOR_DEPTH_888:
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
FMT_DYNAMIC_EXP_EN, 1,
FMT_DYNAMIC_EXP_MODE, 1);
break;
case COLOR_DEPTH_101010:
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
FMT_DYNAMIC_EXP_EN, 1,
FMT_DYNAMIC_EXP_MODE, 0);
break;
case COLOR_DEPTH_121212:
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
FMT_DYNAMIC_EXP_MODE, 0);
break;
default:
break;
}
}
}
static void opp_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
opp_set_clamping(oppn10, params);
set_pixel_encoding(oppn10, params);
}
static void opp_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
/* dithering is affected by <CrtcSourceSelect>, hence should be
* programmed afterwards */
opp_program_bit_depth_reduction(
opp,
fmt_bit_depth);
opp_program_clamping_and_pixel_encoding(
opp,
clamping);
return;
}
static void opp_set_output_csc_default(
struct output_pixel_processor *opp,
const struct default_adjustment *default_adjust)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
uint32_t ocsc_mode = 0;
if (default_adjust != NULL) {
switch (default_adjust->out_color_space) {
case COLOR_SPACE_SRGB:
ocsc_mode = 0;
break;
case COLOR_SPACE_SRGB_LIMITED:
ocsc_mode = 1;
break;
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR601_LIMITED:
ocsc_mode = 2;
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR709_LIMITED:
ocsc_mode = 3;
break;
case COLOR_SPACE_UNKNOWN:
default:
break;
}
}
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
}
/*program re gamma RAM B*/
static void opp_program_regamma_lutb_settings(
struct output_pixel_processor *opp,
const struct pwl_params *params)
{
const struct gamma_curve *curve;
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_SET_2(CM_RGAM_RAMB_START_CNTL_B, 0,
CM_RGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0);
REG_SET_2(CM_RGAM_RAMB_START_CNTL_G, 0,
CM_RGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0);
REG_SET_2(CM_RGAM_RAMB_START_CNTL_R, 0,
CM_RGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0);
REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_B, 0,
CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_G, 0,
CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_R, 0,
CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
REG_SET(CM_RGAM_RAMB_END_CNTL1_B, 0,
CM_RGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
REG_SET_2(CM_RGAM_RAMB_END_CNTL2_B, 0,
CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
CM_RGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
REG_SET(CM_RGAM_RAMB_END_CNTL1_G, 0,
CM_RGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
REG_SET_2(CM_RGAM_RAMB_END_CNTL2_G, 0,
CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
CM_RGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
REG_SET(CM_RGAM_RAMB_END_CNTL1_R, 0,
CM_RGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
REG_SET_2(CM_RGAM_RAMB_END_CNTL2_R, 0,
CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
CM_RGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
curve = params->arr_curve_points;
REG_SET_4(CM_RGAM_RAMB_REGION_0_1, 0,
CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_2_3, 0,
CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_4_5, 0,
CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_6_7, 0,
CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_8_9, 0,
CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_10_11, 0,
CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_12_13, 0,
CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_14_15, 0,
CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_16_17, 0,
CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_18_19, 0,
CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_20_21, 0,
CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_22_23, 0,
CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_24_25, 0,
CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_26_27, 0,
CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_28_29, 0,
CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_30_31, 0,
CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMB_REGION_32_33, 0,
CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
}
/*program re gamma RAM A*/
static void opp_program_regamma_luta_settings(
struct output_pixel_processor *opp,
const struct pwl_params *params)
{
const struct gamma_curve *curve;
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_SET_2(CM_RGAM_RAMA_START_CNTL_B, 0,
CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0);
REG_SET_2(CM_RGAM_RAMA_START_CNTL_G, 0,
CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0);
REG_SET_2(CM_RGAM_RAMA_START_CNTL_R, 0,
CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0);
REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_B, 0,
CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_G, 0,
CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_R, 0,
CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
REG_SET(CM_RGAM_RAMA_END_CNTL1_B, 0,
CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
REG_SET_2(CM_RGAM_RAMA_END_CNTL2_B, 0,
CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
REG_SET(CM_RGAM_RAMA_END_CNTL1_G, 0,
CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
REG_SET_2(CM_RGAM_RAMA_END_CNTL2_G, 0,
CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
REG_SET(CM_RGAM_RAMA_END_CNTL1_R, 0,
CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
REG_SET_2(CM_RGAM_RAMA_END_CNTL2_R, 0,
CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
curve = params->arr_curve_points;
REG_SET_4(CM_RGAM_RAMA_REGION_0_1, 0,
CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_2_3, 0,
CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_4_5, 0,
CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_6_7, 0,
CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_8_9, 0,
CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_10_11, 0,
CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_12_13, 0,
CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_14_15, 0,
CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_16_17, 0,
CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_18_19, 0,
CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_20_21, 0,
CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_22_23, 0,
CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_24_25, 0,
CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_26_27, 0,
CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_28_29, 0,
CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_30_31, 0,
CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
REG_SET_4(CM_RGAM_RAMA_REGION_32_33, 0,
CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
}
static void opp_configure_regamma_lut(
struct output_pixel_processor *opp,
bool is_ram_a)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
CM_RGAM_LUT_WRITE_EN_MASK, 7);
REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
}
static void opp_power_on_regamma_lut(
struct output_pixel_processor *opp,
bool power_on)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_SET(CM_MEM_PWR_CTRL, 0,
RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
}
static void opp_program_regamma_lut(
struct output_pixel_processor *opp,
const struct pwl_result_data *rgb,
uint32_t num)
{
uint32_t i;
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
for (i = 0 ; i < num; i++) {
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
REG_SET(CM_RGAM_LUT_DATA, 0,
CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
REG_SET(CM_RGAM_LUT_DATA, 0,
CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(CM_RGAM_LUT_DATA, 0,
CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
}
}
static bool opp_set_regamma_pwl(
struct output_pixel_processor *opp, const struct pwl_params *params)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
opp_power_on_regamma_lut(opp, true);
opp_configure_regamma_lut(opp, oppn10->is_write_to_ram_a_safe);
if (oppn10->is_write_to_ram_a_safe)
opp_program_regamma_luta_settings(opp, params);
else
opp_program_regamma_lutb_settings(opp, params);
opp_program_regamma_lut(
opp, params->rgb_resulted, params->hw_points_num);
return true;
}
static void opp_set_stereo_polarity(
struct output_pixel_processor *opp,
bool enable, bool rightEyePolarity)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable);
}
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
static void dcn10_opp_destroy(struct output_pixel_processor **opp)
{
dm_free(TO_DCN10_OPP(*opp));
*opp = NULL;
}
static struct opp_funcs dcn10_opp_funcs = {
.opp_power_on_regamma_lut = opp_power_on_regamma_lut,
.opp_set_csc_adjustment = NULL,
.opp_set_csc_default = opp_set_output_csc_default,
.opp_set_dyn_expansion = opp_set_dyn_expansion,
.opp_program_regamma_pwl = opp_set_regamma_pwl,
.opp_set_regamma_mode = opp_set_regamma_mode,
.opp_program_fmt = opp_program_fmt,
.opp_program_bit_depth_reduction = opp_program_bit_depth_reduction,
.opp_set_stereo_polarity = opp_set_stereo_polarity,
.opp_destroy = dcn10_opp_destroy
};
void dcn10_opp_construct(struct dcn10_opp *oppn10,
struct dc_context *ctx,
uint32_t inst,
const struct dcn10_opp_registers *regs,
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask)
{
oppn10->base.ctx = ctx;
oppn10->base.inst = inst;
oppn10->base.funcs = &dcn10_opp_funcs;
oppn10->regs = regs;
oppn10->opp_shift = opp_shift;
oppn10->opp_mask = opp_mask;
}

622
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h Normal file
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@ -0,0 +1,622 @@
/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_OPP_DCN10_H__
#define __DC_OPP_DCN10_H__
#include "opp.h"
#define TO_DCN10_OPP(opp)\
container_of(opp, struct dcn10_opp, base)
#define OPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define OPP_DCN10_REG_LIST(id) \
SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_RGAM_CONTROL, CM, id), \
SRI(OBUF_CONTROL, DSCL, id), \
SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
SRI(FMT_CONTROL, FMT, id), \
SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
SRI(FMT_CLAMP_CNTL, FMT, id), \
SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
SRI(CM_OCSC_CONTROL, CM, id), \
SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
SRI(CM_RGAM_RAMB_REGION_2_3, CM, id), \
SRI(CM_RGAM_RAMB_REGION_4_5, CM, id), \
SRI(CM_RGAM_RAMB_REGION_6_7, CM, id), \
SRI(CM_RGAM_RAMB_REGION_8_9, CM, id), \
SRI(CM_RGAM_RAMB_REGION_10_11, CM, id), \
SRI(CM_RGAM_RAMB_REGION_12_13, CM, id), \
SRI(CM_RGAM_RAMB_REGION_14_15, CM, id), \
SRI(CM_RGAM_RAMB_REGION_16_17, CM, id), \
SRI(CM_RGAM_RAMB_REGION_18_19, CM, id), \
SRI(CM_RGAM_RAMB_REGION_20_21, CM, id), \
SRI(CM_RGAM_RAMB_REGION_22_23, CM, id), \
SRI(CM_RGAM_RAMB_REGION_24_25, CM, id), \
SRI(CM_RGAM_RAMB_REGION_26_27, CM, id), \
SRI(CM_RGAM_RAMB_REGION_28_29, CM, id), \
SRI(CM_RGAM_RAMB_REGION_30_31, CM, id), \
SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
SRI(CM_RGAM_RAMA_REGION_2_3, CM, id), \
SRI(CM_RGAM_RAMA_REGION_4_5, CM, id), \
SRI(CM_RGAM_RAMA_REGION_6_7, CM, id), \
SRI(CM_RGAM_RAMA_REGION_8_9, CM, id), \
SRI(CM_RGAM_RAMA_REGION_10_11, CM, id), \
SRI(CM_RGAM_RAMA_REGION_12_13, CM, id), \
SRI(CM_RGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_RGAM_RAMA_REGION_16_17, CM, id), \
SRI(CM_RGAM_RAMA_REGION_18_19, CM, id), \
SRI(CM_RGAM_RAMA_REGION_20_21, CM, id), \
SRI(CM_RGAM_RAMA_REGION_22_23, CM, id), \
SRI(CM_RGAM_RAMA_REGION_24_25, CM, id), \
SRI(CM_RGAM_RAMA_REGION_26_27, CM, id), \
SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \
SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \
SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
SRI(CM_RGAM_LUT_INDEX, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_RGAM_LUT_DATA, CM, id)
#define OPP_DCN10_MASK_SH_LIST(mask_sh) \
OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \
OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
OPP_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
OPP_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
#define OPP_DCN10_REG_FIELD_LIST(type) \
type CM_RGAM_LUT_MODE; \
type OBUF_BYPASS; \
type OBUF_H_2X_UPSCALE_EN; \
type FMT_TRUNCATE_EN; \
type FMT_TRUNCATE_DEPTH; \
type FMT_TRUNCATE_MODE; \
type FMT_SPATIAL_DITHER_EN; \
type FMT_SPATIAL_DITHER_MODE; \
type FMT_SPATIAL_DITHER_DEPTH; \
type FMT_TEMPORAL_DITHER_EN; \
type FMT_HIGHPASS_RANDOM_ENABLE; \
type FMT_FRAME_RANDOM_ENABLE; \
type FMT_RGB_RANDOM_ENABLE; \
type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
type FMT_RAND_R_SEED; \
type FMT_RAND_G_SEED; \
type FMT_RAND_B_SEED; \
type FMT_PIXEL_ENCODING; \
type FMT_CLAMP_DATA_EN; \
type FMT_CLAMP_COLOR_FORMAT; \
type FMT_DYNAMIC_EXP_EN; \
type FMT_DYNAMIC_EXP_MODE; \
type FMT_MAP420MEM_PWR_FORCE; \
type CM_OCSC_MODE; \
type CM_RGAM_RAMB_EXP_REGION_START_B; \
type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
type CM_RGAM_RAMB_EXP_REGION_START_G; \
type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
type CM_RGAM_RAMB_EXP_REGION_START_R; \
type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
type CM_RGAM_RAMB_EXP_REGION_END_B; \
type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
type CM_RGAM_RAMB_EXP_REGION_END_G; \
type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
type CM_RGAM_RAMB_EXP_REGION_END_R; \
type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION_START_B; \
type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
type CM_RGAM_RAMA_EXP_REGION_START_G; \
type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
type CM_RGAM_RAMA_EXP_REGION_START_R; \
type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
type CM_RGAM_RAMA_EXP_REGION_END_B; \
type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
type CM_RGAM_RAMA_EXP_REGION_END_G; \
type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
type CM_RGAM_RAMA_EXP_REGION_END_R; \
type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
type CM_RGAM_LUT_WRITE_EN_MASK; \
type CM_RGAM_LUT_WRITE_SEL; \
type CM_RGAM_LUT_INDEX; \
type RGAM_MEM_PWR_FORCE; \
type CM_RGAM_LUT_DATA; \
type FMT_STEREOSYNC_OVERRIDE
struct dcn10_opp_shift {
OPP_DCN10_REG_FIELD_LIST(uint8_t);
};
struct dcn10_opp_mask {
OPP_DCN10_REG_FIELD_LIST(uint32_t);
};
struct dcn10_opp_registers {
uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
uint32_t CM_RGAM_CONTROL;
uint32_t OBUF_CONTROL;
uint32_t FMT_BIT_DEPTH_CONTROL;
uint32_t FMT_CONTROL;
uint32_t FMT_DITHER_RAND_R_SEED;
uint32_t FMT_DITHER_RAND_G_SEED;
uint32_t FMT_DITHER_RAND_B_SEED;
uint32_t FMT_CLAMP_CNTL;
uint32_t FMT_DYNAMIC_EXP_CNTL;
uint32_t FMT_MAP420_MEMORY_CONTROL;
uint32_t CM_OCSC_CONTROL;
uint32_t CM_RGAM_RAMB_START_CNTL_B;
uint32_t CM_RGAM_RAMB_START_CNTL_G;
uint32_t CM_RGAM_RAMB_START_CNTL_R;
uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
uint32_t CM_RGAM_RAMB_END_CNTL1_B;
uint32_t CM_RGAM_RAMB_END_CNTL2_B;
uint32_t CM_RGAM_RAMB_END_CNTL1_G;
uint32_t CM_RGAM_RAMB_END_CNTL2_G;
uint32_t CM_RGAM_RAMB_END_CNTL1_R;
uint32_t CM_RGAM_RAMB_END_CNTL2_R;
uint32_t CM_RGAM_RAMB_REGION_0_1;
uint32_t CM_RGAM_RAMB_REGION_2_3;
uint32_t CM_RGAM_RAMB_REGION_4_5;
uint32_t CM_RGAM_RAMB_REGION_6_7;
uint32_t CM_RGAM_RAMB_REGION_8_9;
uint32_t CM_RGAM_RAMB_REGION_10_11;
uint32_t CM_RGAM_RAMB_REGION_12_13;
uint32_t CM_RGAM_RAMB_REGION_14_15;
uint32_t CM_RGAM_RAMB_REGION_16_17;
uint32_t CM_RGAM_RAMB_REGION_18_19;
uint32_t CM_RGAM_RAMB_REGION_20_21;
uint32_t CM_RGAM_RAMB_REGION_22_23;
uint32_t CM_RGAM_RAMB_REGION_24_25;
uint32_t CM_RGAM_RAMB_REGION_26_27;
uint32_t CM_RGAM_RAMB_REGION_28_29;
uint32_t CM_RGAM_RAMB_REGION_30_31;
uint32_t CM_RGAM_RAMB_REGION_32_33;
uint32_t CM_RGAM_RAMA_START_CNTL_B;
uint32_t CM_RGAM_RAMA_START_CNTL_G;
uint32_t CM_RGAM_RAMA_START_CNTL_R;
uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
uint32_t CM_RGAM_RAMA_END_CNTL1_B;
uint32_t CM_RGAM_RAMA_END_CNTL2_B;
uint32_t CM_RGAM_RAMA_END_CNTL1_G;
uint32_t CM_RGAM_RAMA_END_CNTL2_G;
uint32_t CM_RGAM_RAMA_END_CNTL1_R;
uint32_t CM_RGAM_RAMA_END_CNTL2_R;
uint32_t CM_RGAM_RAMA_REGION_0_1;
uint32_t CM_RGAM_RAMA_REGION_2_3;
uint32_t CM_RGAM_RAMA_REGION_4_5;
uint32_t CM_RGAM_RAMA_REGION_6_7;
uint32_t CM_RGAM_RAMA_REGION_8_9;
uint32_t CM_RGAM_RAMA_REGION_10_11;
uint32_t CM_RGAM_RAMA_REGION_12_13;
uint32_t CM_RGAM_RAMA_REGION_14_15;
uint32_t CM_RGAM_RAMA_REGION_16_17;
uint32_t CM_RGAM_RAMA_REGION_18_19;
uint32_t CM_RGAM_RAMA_REGION_20_21;
uint32_t CM_RGAM_RAMA_REGION_22_23;
uint32_t CM_RGAM_RAMA_REGION_24_25;
uint32_t CM_RGAM_RAMA_REGION_26_27;
uint32_t CM_RGAM_RAMA_REGION_28_29;
uint32_t CM_RGAM_RAMA_REGION_30_31;
uint32_t CM_RGAM_RAMA_REGION_32_33;
uint32_t CM_RGAM_LUT_INDEX;
uint32_t CM_MEM_PWR_CTRL;
uint32_t CM_RGAM_LUT_DATA;
};
struct dcn10_opp {
struct output_pixel_processor base;
const struct dcn10_opp_registers *regs;
const struct dcn10_opp_shift *opp_shift;
const struct dcn10_opp_mask *opp_mask;
bool is_write_to_ram_a_safe;
};
void dcn10_opp_construct(struct dcn10_opp *oppn10,
struct dc_context *ctx,
uint32_t inst,
const struct dcn10_opp_registers *regs,
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask);
#endif

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c Normal file
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_RESOURCE_DCN10_H__
#define __DC_RESOURCE_DCN10_H__
#include "core_types.h"
#define TO_DCN10_RES_POOL(pool)\
container_of(pool, struct dcn10_resource_pool, base)
struct core_dc;
struct resource_pool;
struct _vcs_dpi_display_pipe_params_st;
struct dcn10_resource_pool {
struct resource_pool base;
};
struct resource_pool *dcn10_create_resource_pool(
uint8_t num_virtual_links,
struct core_dc *dc);
#endif /* __DC_RESOURCE_DCN10_H__ */

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_TIMING_GENERATOR_DCN10_H__
#define __DC_TIMING_GENERATOR_DCN10_H__
#include "timing_generator.h"
#define DCN10TG_FROM_TG(tg)\
container_of(tg, struct dcn10_timing_generator, base)
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
SRI(OTG_VREADY_PARAM, OTG, inst),\
SRI(OTG_BLANK_CONTROL, OTG, inst),\
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
SRI(OTG_H_TOTAL, OTG, inst),\
SRI(OTG_H_BLANK_START_END, OTG, inst),\
SRI(OTG_H_SYNC_A, OTG, inst),\
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
SRI(OTG_V_TOTAL, OTG, inst),\
SRI(OTG_V_BLANK_START_END, OTG, inst),\
SRI(OTG_V_SYNC_A, OTG, inst),\
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
SRI(OTG_CONTROL, OTG, inst),\
SRI(OTG_STEREO_CONTROL, OTG, inst),\
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
SRI(OTG_TRIGA_CNTL, OTG, inst),\
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
SRI(OTG_STATUS, OTG, inst),\
SRI(OTG_STATUS_POSITION, OTG, inst),\
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
SRI(OTG_BLACK_COLOR, OTG, inst),\
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
SRI(OPPBUF_CONTROL, OPPBUF, inst),\
SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\
SRI(CONTROL, VTG, inst),\
SR(D1VGA_CONTROL),\
SR(D2VGA_CONTROL),\
SR(D3VGA_CONTROL),\
SR(D4VGA_CONTROL),\
struct dcn_tg_registers {
uint32_t OTG_VSTARTUP_PARAM;
uint32_t OTG_VUPDATE_PARAM;
uint32_t OTG_VREADY_PARAM;
uint32_t OTG_BLANK_CONTROL;
uint32_t OTG_MASTER_UPDATE_LOCK;
uint32_t OTG_DOUBLE_BUFFER_CONTROL;
uint32_t OTG_H_TOTAL;
uint32_t OTG_H_BLANK_START_END;
uint32_t OTG_H_SYNC_A;
uint32_t OTG_H_SYNC_A_CNTL;
uint32_t OTG_H_TIMING_CNTL;
uint32_t OTG_V_TOTAL;
uint32_t OTG_V_BLANK_START_END;
uint32_t OTG_V_SYNC_A;
uint32_t OTG_V_SYNC_A_CNTL;
uint32_t OTG_INTERLACE_CONTROL;
uint32_t OTG_CONTROL;
uint32_t OTG_STEREO_CONTROL;
uint32_t OTG_3D_STRUCTURE_CONTROL;
uint32_t OTG_V_TOTAL_MAX;
uint32_t OTG_V_TOTAL_MIN;
uint32_t OTG_V_TOTAL_CONTROL;
uint32_t OTG_TRIGA_CNTL;
uint32_t OTG_FORCE_COUNT_NOW_CNTL;
uint32_t OTG_STATIC_SCREEN_CONTROL;
uint32_t OTG_STATUS_FRAME_COUNT;
uint32_t OTG_STATUS;
uint32_t OTG_STATUS_POSITION;
uint32_t OTG_NOM_VERT_POSITION;
uint32_t OTG_BLACK_COLOR;
uint32_t OTG_TEST_PATTERN_PARAMETERS;
uint32_t OTG_TEST_PATTERN_CONTROL;
uint32_t OTG_TEST_PATTERN_COLOR;
uint32_t OTG_CLOCK_CONTROL;
uint32_t OPTC_INPUT_CLOCK_CONTROL;
uint32_t OPTC_DATA_SOURCE_SELECT;
uint32_t OPPBUF_CONTROL;
uint32_t OPPBUF_3D_PARAMETERS_0;
uint32_t CONTROL;
/*todo: move VGA to HWSS */
uint32_t D1VGA_CONTROL;
uint32_t D2VGA_CONTROL;
uint32_t D3VGA_CONTROL;
uint32_t D4VGA_CONTROL;
};
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
#define TG_REG_FIELD_LIST(type) \
type VSTARTUP_START;\
type VUPDATE_OFFSET;\
type VUPDATE_WIDTH;\
type VREADY_OFFSET;\
type OTG_BLANK_DATA_EN;\
type OTG_BLANK_DE_MODE;\
type OTG_CURRENT_BLANK_STATE;\
type OTG_MASTER_UPDATE_LOCK;\
type OTG_UPDATE_PENDING;\
type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
type OTG_H_TOTAL;\
type OTG_H_BLANK_START;\
type OTG_H_BLANK_END;\
type OTG_H_SYNC_A_START;\
type OTG_H_SYNC_A_END;\
type OTG_H_SYNC_A_POL;\
type OTG_H_TIMING_DIV_BY2;\
type OTG_V_TOTAL;\
type OTG_V_BLANK_START;\
type OTG_V_BLANK_END;\
type OTG_V_SYNC_A_START;\
type OTG_V_SYNC_A_END;\
type OTG_V_SYNC_A_POL;\
type OTG_INTERLACE_ENABLE;\
type OTG_MASTER_EN;\
type OTG_START_POINT_CNTL;\
type OTG_DISABLE_POINT_CNTL;\
type OTG_FIELD_NUMBER_CNTL;\
type OTG_STEREO_EN;\
type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
type OTG_STEREO_EYE_FLAG_POLARITY;\
type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
type OTG_3D_STRUCTURE_EN;\
type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
type OTG_V_TOTAL_MAX;\
type OTG_V_TOTAL_MIN;\
type OTG_V_TOTAL_MIN_SEL;\
type OTG_V_TOTAL_MAX_SEL;\
type OTG_FORCE_LOCK_ON_EVENT;\
type OTG_SET_V_TOTAL_MIN_MASK_EN;\
type OTG_SET_V_TOTAL_MIN_MASK;\
type OTG_FORCE_COUNT_NOW_CLEAR;\
type OTG_FORCE_COUNT_NOW_MODE;\
type OTG_FORCE_COUNT_NOW_OCCURRED;\
type OTG_TRIGA_SOURCE_SELECT;\
type OTG_TRIGA_SOURCE_PIPE_SELECT;\
type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
type OTG_STATIC_SCREEN_EVENT_MASK;\
type OTG_STATIC_SCREEN_FRAME_COUNT;\
type OTG_FRAME_COUNT;\
type OTG_V_BLANK;\
type OTG_V_ACTIVE_DISP;\
type OTG_HORZ_COUNT;\
type OTG_VERT_COUNT;\
type OTG_VERT_COUNT_NOM;\
type OTG_BLACK_COLOR_B_CB;\
type OTG_BLACK_COLOR_G_Y;\
type OTG_BLACK_COLOR_R_CR;\
type OTG_TEST_PATTERN_INC0;\
type OTG_TEST_PATTERN_INC1;\
type OTG_TEST_PATTERN_VRES;\
type OTG_TEST_PATTERN_HRES;\
type OTG_TEST_PATTERN_RAMP0_OFFSET;\
type OTG_TEST_PATTERN_EN;\
type OTG_TEST_PATTERN_MODE;\
type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
type OTG_TEST_PATTERN_COLOR_FORMAT;\
type OTG_TEST_PATTERN_MASK;\
type OTG_TEST_PATTERN_DATA;\
type OTG_BUSY;\
type OTG_CLOCK_EN;\
type OTG_CLOCK_ON;\
type OTG_CLOCK_GATE_DIS;\
type OPTC_INPUT_CLK_EN;\
type OPTC_INPUT_CLK_ON;\
type OPTC_INPUT_CLK_GATE_DIS;\
type OPTC_SRC_SEL;\
type OPPBUF_ACTIVE_WIDTH;\
type OPPBUF_3D_VACT_SPACE1_SIZE;\
type VTG0_ENABLE;\
type VTG0_FP2;\
type VTG0_VCOUNT_INIT;\
struct dcn_tg_shift {
TG_REG_FIELD_LIST(uint8_t)
};
struct dcn_tg_mask {
TG_REG_FIELD_LIST(uint32_t)
};
struct dcn10_timing_generator {
struct timing_generator base;
const struct dcn_tg_registers *tg_regs;
const struct dcn_tg_shift *tg_shift;
const struct dcn_tg_mask *tg_mask;
enum controller_id controller_id;
uint32_t max_h_total;
uint32_t max_v_total;
uint32_t min_h_blank;
uint32_t min_h_sync_width;
uint32_t min_v_sync_width;
uint32_t min_v_blank;
uint32_t min_v_blank_interlace;
};
void dcn10_timing_generator_init(struct dcn10_timing_generator *tg);
void dcn10_timing_generator_set_drr(struct timing_generator *tg,
const struct drr_params *params);
void dcn10_unlock(struct timing_generator *tg);
void dcn10_lock(struct timing_generator *tg);
#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */

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/* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_TRANSFORM_DCN10_H__
#define __DAL_TRANSFORM_DCN10_H__
#include "transform.h"
#define TO_DCN10_TRANSFORM(transform)\
container_of(transform, struct dcn10_transform, base)
/* TODO: Use correct number of taps. Using polaris values for now */
#define LB_TOTAL_NUMBER_OF_ENTRIES 5124
#define LB_BITS_PER_ENTRY 144
#define TF_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define TF_REG_LIST_DCN(id) \
SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
SRI(OTG_H_BLANK, DSCL, id), \
SRI(OTG_V_BLANK, DSCL, id), \
SRI(SCL_MODE, DSCL, id), \
SRI(LB_DATA_FORMAT, DSCL, id), \
SRI(LB_MEMORY_CTRL, DSCL, id), \
SRI(DSCL_AUTOCAL, DSCL, id), \
SRI(SCL_BLACK_OFFSET, DSCL, id), \
SRI(DSCL_CONTROL, DSCL, id), \
SRI(SCL_TAP_CONTROL, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI(DSCL_2TAP_CONTROL, DSCL, id), \
SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
SRI(CM_GAMUT_REMAP_CONTROL, CM, id), \
SRI(MPC_SIZE, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
SRI(RECOUT_START, DSCL, id), \
SRI(RECOUT_SIZE, DSCL, id), \
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI(CM_COMA_C11_C12, CM, id),\
SRI(CM_COMA_C13_C14, CM, id),\
SRI(CM_COMA_C21_C22, CM, id),\
SRI(CM_COMA_C23_C24, CM, id),\
SRI(CM_COMA_C31_C32, CM, id),\
SRI(CM_COMA_C33_C34, CM, id),\
SRI(CM_COMB_C11_C12, CM, id),\
SRI(CM_COMB_C13_C14, CM, id),\
SRI(CM_COMB_C21_C22, CM, id),\
SRI(CM_COMB_C23_C24, CM, id),\
SRI(CM_COMB_C31_C32, CM, id),\
SRI(CM_COMB_C33_C34, CM, id)
#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, ALPHA_EN, mask_sh),\
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
TF_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh),\
TF_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh),\
TF_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh),\
TF_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh),\
TF_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh),\
TF_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh),\
TF_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh),\
TF_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh),\
TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
TF_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh),\
TF_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh),\
TF_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh),\
TF_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh),\
TF_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh),\
TF_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh),\
TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh),\
TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh),\
TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh)
#define TF_REG_FIELD_LIST(type) \
type EXT_OVERSCAN_LEFT; \
type EXT_OVERSCAN_RIGHT; \
type EXT_OVERSCAN_BOTTOM; \
type EXT_OVERSCAN_TOP; \
type OTG_H_BLANK_START; \
type OTG_H_BLANK_END; \
type OTG_V_BLANK_START; \
type OTG_V_BLANK_END; \
type PIXEL_DEPTH; \
type PIXEL_EXPAN_MODE; \
type PIXEL_REDUCE_MODE; \
type DYNAMIC_PIXEL_DEPTH; \
type DITHER_EN; \
type INTERLEAVE_EN; \
type ALPHA_EN; \
type MEMORY_CONFIG; \
type LB_MAX_PARTITIONS; \
type AUTOCAL_MODE; \
type AUTOCAL_NUM_PIPE; \
type AUTOCAL_PIPE_ID; \
type SCL_BLACK_OFFSET_RGB_Y; \
type SCL_BLACK_OFFSET_CBCR; \
type SCL_BOUNDARY_MODE; \
type SCL_V_NUM_TAPS; \
type SCL_H_NUM_TAPS; \
type SCL_V_NUM_TAPS_C; \
type SCL_H_NUM_TAPS_C; \
type SCL_COEF_RAM_TAP_PAIR_IDX; \
type SCL_COEF_RAM_PHASE; \
type SCL_COEF_RAM_FILTER_TYPE; \
type SCL_COEF_RAM_EVEN_TAP_COEF; \
type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
type SCL_COEF_RAM_ODD_TAP_COEF; \
type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
type SCL_H_2TAP_HARDCODE_COEF_EN; \
type SCL_H_2TAP_SHARP_EN; \
type SCL_H_2TAP_SHARP_FACTOR; \
type SCL_V_2TAP_HARDCODE_COEF_EN; \
type SCL_V_2TAP_SHARP_EN; \
type SCL_V_2TAP_SHARP_FACTOR; \
type SCL_COEF_RAM_SELECT; \
type PRI_VIEWPORT_WIDTH; \
type PRI_VIEWPORT_HEIGHT; \
type PRI_VIEWPORT_X_START; \
type PRI_VIEWPORT_Y_START; \
type SEC_VIEWPORT_WIDTH; \
type SEC_VIEWPORT_HEIGHT; \
type SEC_VIEWPORT_X_START; \
type SEC_VIEWPORT_Y_START; \
type PRI_VIEWPORT_WIDTH_C; \
type PRI_VIEWPORT_HEIGHT_C; \
type PRI_VIEWPORT_X_START_C; \
type PRI_VIEWPORT_Y_START_C; \
type DSCL_MODE; \
type RECOUT_START_X; \
type RECOUT_START_Y; \
type RECOUT_WIDTH; \
type RECOUT_HEIGHT; \
type MPC_WIDTH; \
type MPC_HEIGHT; \
type SCL_H_SCALE_RATIO; \
type SCL_V_SCALE_RATIO; \
type SCL_H_SCALE_RATIO_C; \
type SCL_V_SCALE_RATIO_C; \
type SCL_H_INIT_FRAC; \
type SCL_H_INIT_INT; \
type SCL_H_INIT_FRAC_C; \
type SCL_H_INIT_INT_C; \
type SCL_V_INIT_FRAC; \
type SCL_V_INIT_INT; \
type SCL_V_INIT_FRAC_BOT; \
type SCL_V_INIT_INT_BOT; \
type SCL_V_INIT_FRAC_C; \
type SCL_V_INIT_INT_C; \
type SCL_V_INIT_FRAC_BOT_C; \
type SCL_V_INIT_INT_BOT_C; \
type SCL_CHROMA_COEF_MODE; \
type SCL_COEF_RAM_SELECT_CURRENT; \
type CM_GAMUT_REMAP_MODE; \
type CM_GAMUT_REMAP_C11; \
type CM_GAMUT_REMAP_C12; \
type CM_GAMUT_REMAP_C13; \
type CM_GAMUT_REMAP_C14; \
type CM_GAMUT_REMAP_C21; \
type CM_GAMUT_REMAP_C22; \
type CM_GAMUT_REMAP_C23; \
type CM_GAMUT_REMAP_C24; \
type CM_GAMUT_REMAP_C31; \
type CM_GAMUT_REMAP_C32; \
type CM_GAMUT_REMAP_C33; \
type CM_GAMUT_REMAP_C34; \
type CM_COMA_C11; \
type CM_COMA_C12; \
type CM_COMA_C13; \
type CM_COMA_C14; \
type CM_COMA_C21; \
type CM_COMA_C22; \
type CM_COMA_C23; \
type CM_COMA_C24; \
type CM_COMA_C31; \
type CM_COMA_C32; \
type CM_COMA_C33; \
type CM_COMA_C34; \
type CM_COMB_C11; \
type CM_COMB_C12; \
type CM_COMB_C13; \
type CM_COMB_C14; \
type CM_COMB_C21; \
type CM_COMB_C22; \
type CM_COMB_C23; \
type CM_COMB_C24; \
type CM_COMB_C31; \
type CM_COMB_C32; \
type CM_COMB_C33; \
type CM_COMB_C34
struct dcn_transform_shift {
TF_REG_FIELD_LIST(uint8_t);
};
struct dcn_transform_mask {
TF_REG_FIELD_LIST(uint32_t);
};
struct dcn_transform_registers {
uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
uint32_t OTG_H_BLANK;
uint32_t OTG_V_BLANK;
uint32_t SCL_MODE;
uint32_t LB_DATA_FORMAT;
uint32_t LB_MEMORY_CTRL;
uint32_t DSCL_AUTOCAL;
uint32_t SCL_BLACK_OFFSET;
uint32_t DSCL_CONTROL;
uint32_t SCL_TAP_CONTROL;
uint32_t SCL_COEF_RAM_TAP_SELECT;
uint32_t SCL_COEF_RAM_TAP_DATA;
uint32_t DSCL_2TAP_CONTROL;
uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
uint32_t DCSURF_PRI_VIEWPORT_START;
uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
uint32_t DCSURF_SEC_VIEWPORT_START;
uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
uint32_t DCSURF_PRI_VIEWPORT_START_C;
uint32_t MPC_SIZE;
uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
uint32_t SCL_VERT_FILTER_SCALE_RATIO;
uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C;
uint32_t SCL_VERT_FILTER_SCALE_RATIO_C;
uint32_t SCL_HORZ_FILTER_INIT;
uint32_t SCL_HORZ_FILTER_INIT_C;
uint32_t SCL_VERT_FILTER_INIT;
uint32_t SCL_VERT_FILTER_INIT_BOT;
uint32_t SCL_VERT_FILTER_INIT_C;
uint32_t SCL_VERT_FILTER_INIT_BOT_C;
uint32_t RECOUT_START;
uint32_t RECOUT_SIZE;
uint32_t CM_GAMUT_REMAP_CONTROL;
uint32_t CM_GAMUT_REMAP_C11_C12;
uint32_t CM_GAMUT_REMAP_C13_C14;
uint32_t CM_GAMUT_REMAP_C21_C22;
uint32_t CM_GAMUT_REMAP_C23_C24;
uint32_t CM_GAMUT_REMAP_C31_C32;
uint32_t CM_GAMUT_REMAP_C33_C34;
uint32_t CM_COMA_C11_C12;
uint32_t CM_COMA_C13_C14;
uint32_t CM_COMA_C21_C22;
uint32_t CM_COMA_C23_C24;
uint32_t CM_COMA_C31_C32;
uint32_t CM_COMA_C33_C34;
uint32_t CM_COMB_C11_C12;
uint32_t CM_COMB_C13_C14;
uint32_t CM_COMB_C21_C22;
uint32_t CM_COMB_C23_C24;
uint32_t CM_COMB_C31_C32;
uint32_t CM_COMB_C33_C34;
};
struct dcn10_transform {
struct transform base;
const struct dcn_transform_registers *tf_regs;
const struct dcn_transform_shift *tf_shift;
const struct dcn_transform_mask *tf_mask;
const uint16_t *filter_v;
const uint16_t *filter_h;
const uint16_t *filter_v_c;
const uint16_t *filter_h_c;
int lb_pixel_depth_supported;
int lb_memory_size;
int lb_bits_per_entry;
};
bool dcn10_transform_construct(struct dcn10_transform *xfm110,
struct dc_context *ctx,
const struct dcn_transform_registers *tf_regs,
const struct dcn_transform_shift *tf_shift,
const struct dcn_transform_mask *tf_mask);
#endif