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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: ethernet: mediatek: Integrate hardware path from GMAC to PHY variants
All path route on various SoCs all would be managed in common function mtk_setup_hw_path that is determined by the both applied devicetree regarding the path between GMAC and the target PHY or switch by the capability of target SoC in the runtime. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sean Wang
David S. Miller
parent
9ffee4a827
commit
7093f9d80c
@ -3,4 +3,5 @@
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# Makefile for the Mediatek SoCs built-in ethernet macs
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#
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth_soc.o mtk_sgmii.o
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth_soc.o mtk_sgmii.o \
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mtk_eth_path.o
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323
drivers/net/ethernet/mediatek/mtk_eth_path.c
Normal file
323
drivers/net/ethernet/mediatek/mtk_eth_path.c
Normal file
@ -0,0 +1,323 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018-2019 MediaTek Inc.
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/* A library for configuring path from GMAC/GDM to target PHY
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include "mtk_eth_soc.h"
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struct mtk_eth_muxc {
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int (*set_path)(struct mtk_eth *eth, int path);
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};
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static const char * const mtk_eth_mux_name[] = {
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"mux_gdm1_to_gmac1_esw", "mux_gmac2_gmac0_to_gephy",
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"mux_u3_gmac2_to_qphy", "mux_gmac1_gmac2_to_sgmii_rgmii",
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"mux_gmac12_to_gephy_sgmii",
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};
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static const char * const mtk_eth_path_name[] = {
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"gmac1_rgmii", "gmac1_trgmii", "gmac1_sgmii", "gmac2_rgmii",
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"gmac2_sgmii", "gmac2_gephy", "gdm1_esw",
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};
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static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path)
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{
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bool updated = true;
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u32 val, mask, set;
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switch (path) {
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case MTK_ETH_PATH_GMAC1_SGMII:
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mask = ~(u32)MTK_MUX_TO_ESW;
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set = 0;
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break;
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case MTK_ETH_PATH_GDM1_ESW:
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mask = ~(u32)MTK_MUX_TO_ESW;
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set = MTK_MUX_TO_ESW;
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break;
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default:
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updated = false;
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break;
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};
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if (updated) {
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val = mtk_r32(eth, MTK_MAC_MISC);
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val = (val & mask) | set;
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mtk_w32(eth, val, MTK_MAC_MISC);
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}
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name[path], __func__, updated);
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return 0;
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}
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static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path)
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{
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unsigned int val = 0;
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bool updated = true;
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switch (path) {
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case MTK_ETH_PATH_GMAC2_GEPHY:
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val = ~(u32)GEPHY_MAC_SEL;
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break;
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default:
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updated = false;
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break;
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}
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if (updated)
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regmap_update_bits(eth->infra, INFRA_MISC2, GEPHY_MAC_SEL, val);
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name[path], __func__, updated);
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return 0;
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}
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static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
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{
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unsigned int val = 0;
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bool updated = true;
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switch (path) {
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case MTK_ETH_PATH_GMAC2_SGMII:
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val = CO_QPHY_SEL;
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break;
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default:
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updated = false;
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break;
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}
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if (updated)
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regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val);
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name[path], __func__, updated);
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return 0;
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}
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static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path)
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{
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unsigned int val = 0;
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bool updated = true;
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switch (path) {
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case MTK_ETH_PATH_GMAC1_SGMII:
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val = SYSCFG0_SGMII_GMAC1;
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break;
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case MTK_ETH_PATH_GMAC2_SGMII:
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val = SYSCFG0_SGMII_GMAC2;
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break;
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case MTK_ETH_PATH_GMAC1_RGMII:
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case MTK_ETH_PATH_GMAC2_RGMII:
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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val &= SYSCFG0_SGMII_MASK;
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if ((path == MTK_GMAC1_RGMII && val == SYSCFG0_SGMII_GMAC1) ||
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(path == MTK_GMAC2_RGMII && val == SYSCFG0_SGMII_GMAC2))
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val = 0;
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else
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updated = false;
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break;
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default:
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updated = false;
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break;
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};
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if (updated)
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regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
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SYSCFG0_SGMII_MASK, val);
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name[path], __func__, updated);
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return 0;
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}
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static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path)
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{
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unsigned int val = 0;
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bool updated = true;
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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switch (path) {
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case MTK_ETH_PATH_GMAC1_SGMII:
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val |= SYSCFG0_SGMII_GMAC1_V2;
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break;
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case MTK_ETH_PATH_GMAC2_GEPHY:
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val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
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break;
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case MTK_ETH_PATH_GMAC2_SGMII:
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val |= SYSCFG0_SGMII_GMAC2_V2;
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break;
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default:
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updated = false;
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};
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if (updated)
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regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
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SYSCFG0_SGMII_MASK, val);
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name[path], __func__, updated);
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return 0;
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}
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static const struct mtk_eth_muxc mtk_eth_muxc[] = {
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{ .set_path = set_mux_gdm1_to_gmac1_esw, },
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{ .set_path = set_mux_gmac2_gmac0_to_gephy, },
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{ .set_path = set_mux_u3_gmac2_to_qphy, },
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{ .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, },
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{ .set_path = set_mux_gmac12_to_gephy_sgmii, }
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};
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static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)
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{
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int i, err = 0;
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if (!MTK_HAS_CAPS(eth->soc->caps, MTK_PATH_BIT(path))) {
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dev_err(eth->dev, "path %s isn't support on the SoC\n",
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mtk_eth_path_name[path]);
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return -EINVAL;
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}
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if (!MTK_HAS_CAPS(eth->soc->caps, MTK_MUX))
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return 0;
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/* Setup MUX in path fabric */
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for (i = 0; i < MTK_ETH_MUX_MAX; i++) {
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_MUX_BIT(i))) {
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err = mtk_eth_muxc[i].set_path(eth, path);
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if (err)
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goto out;
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} else {
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dev_dbg(eth->dev, "mux %s isn't present on the SoC\n",
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mtk_eth_mux_name[i]);
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}
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}
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out:
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return err;
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}
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static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
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{
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unsigned int val = 0;
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int sid, err, path;
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path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
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MTK_ETH_PATH_GMAC2_SGMII;
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/* Setup proper MUXes along the path */
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err = mtk_eth_mux_setup(eth, path);
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if (err)
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return err;
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/* The path GMAC to SGMII will be enabled once the SGMIISYS is being
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* setup done.
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*/
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
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SYSCFG0_SGMII_MASK, ~(u32)SYSCFG0_SGMII_MASK);
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/* Decide how GMAC and SGMIISYS be mapped */
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sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 0 : mac_id;
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/* Setup SGMIISYS with the determined property */
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if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN))
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err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
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else
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err = mtk_sgmii_setup_mode_force(eth->sgmii, sid);
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if (err)
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return err;
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regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
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SYSCFG0_SGMII_MASK, val);
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return 0;
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}
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static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
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{
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int err, path = 0;
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if (mac_id == 1)
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path = MTK_ETH_PATH_GMAC2_GEPHY;
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if (!path)
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return -EINVAL;
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/* Setup proper MUXes along the path */
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err = mtk_eth_mux_setup(eth, path);
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if (err)
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return err;
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return 0;
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}
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static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
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{
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int err, path;
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path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_RGMII :
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MTK_ETH_PATH_GMAC2_RGMII;
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/* Setup proper MUXes along the path */
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err = mtk_eth_mux_setup(eth, path);
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if (err)
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return err;
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return 0;
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}
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int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode)
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{
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int err;
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switch (phymode) {
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case PHY_INTERFACE_MODE_TRGMII:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_REVMII:
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case PHY_INTERFACE_MODE_RMII:
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
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err = mtk_gmac_rgmii_path_setup(eth, mac_id);
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if (err)
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return err;
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}
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break;
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case PHY_INTERFACE_MODE_SGMII:
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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err = mtk_gmac_sgmii_path_setup(eth, mac_id);
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if (err)
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return err;
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}
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break;
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case PHY_INTERFACE_MODE_GMII:
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
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err = mtk_gmac_gephy_path_setup(eth, mac_id);
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if (err)
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return err;
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}
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break;
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default:
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break;
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}
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return 0;
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}
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@ -165,50 +165,6 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
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mtk_w32(eth, val, TRGMII_TCK_CTRL);
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}
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static int mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
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{
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int sid, err;
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u32 val;
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/* Enable GMAC with SGMII once we finish the SGMII setup. */
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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val &= ~SYSCFG0_SGMII_MASK;
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regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC_SHARED_SGMII))
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sid = 0;
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else
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sid = mac_id;
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if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN))
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err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
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else
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err = mtk_sgmii_setup_mode_force(eth->sgmii, sid);
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if (err)
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return err;
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/* Determine MUX for which GMAC uses the SGMII interface */
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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if (!mac_id)
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val |= SYSCFG0_SGMII_GMAC1;
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else
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val |= MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC_SHARED_SGMII) ?
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SYSCFG0_SGMII_GMAC2 : SYSCFG0_SGMII_GMAC2_V2;
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regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
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/* Setup the GMAC1 going through SGMII path when SoC also support
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* ESW on GMAC1
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*/
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
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!mac_id) {
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mtk_w32(eth, 0, MTK_MAC_MISC);
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dev_info(eth->dev, "setup gmac1 going through sgmii");
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}
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return 0;
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}
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static void mtk_phy_link_adjust(struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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@ -308,6 +264,10 @@ static int mtk_phy_connect(struct net_device *dev)
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if (!np)
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return -ENODEV;
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err = mtk_setup_hw_path(eth, mac->id, of_get_phy_mode(np));
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if (err)
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goto err_phy;
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mac->ge_mode = 0;
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switch (of_get_phy_mode(np)) {
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case PHY_INTERFACE_MODE_TRGMII:
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@ -316,15 +276,10 @@ static int mtk_phy_connect(struct net_device *dev)
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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break;
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case PHY_INTERFACE_MODE_SGMII:
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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err = mtk_gmac_sgmii_hw_setup(eth, mac->id);
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if (err)
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goto err_phy;
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}
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break;
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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mac->ge_mode = 1;
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break;
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case PHY_INTERFACE_MODE_REVMII:
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@ -2489,6 +2444,15 @@ static int mtk_probe(struct platform_device *pdev)
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return PTR_ERR(eth->ethsys);
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
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eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"mediatek,infracfg");
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if (IS_ERR(eth->infra)) {
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dev_err(&pdev->dev, "no infracfg regmap found\n");
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return PTR_ERR(eth->infra);
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}
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
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GFP_KERNEL);
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@ -2640,7 +2604,7 @@ static int mtk_remove(struct platform_device *pdev)
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}
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static const struct mtk_soc_data mt2701_data = {
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.caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
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.caps = MT7623_CAPS | MTK_HWLRO,
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.required_clks = MT7623_CLKS_BITMAP,
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.required_pctl = true,
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};
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@ -2653,13 +2617,13 @@ static const struct mtk_soc_data mt7621_data = {
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|
||||
static const struct mtk_soc_data mt7622_data = {
|
||||
.ana_rgc3 = 0x2028,
|
||||
.caps = MTK_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
|
||||
.caps = MT7622_CAPS | MTK_HWLRO,
|
||||
.required_clks = MT7622_CLKS_BITMAP,
|
||||
.required_pctl = false,
|
||||
};
|
||||
|
||||
static const struct mtk_soc_data mt7623_data = {
|
||||
.caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
|
||||
.caps = MT7623_CAPS | MTK_HWLRO,
|
||||
.required_clks = MT7623_CLKS_BITMAP,
|
||||
.required_pctl = true,
|
||||
};
|
||||
|
||||
@ -373,10 +373,12 @@
|
||||
#define ETHSYS_SYSCFG0 0x14
|
||||
#define SYSCFG0_GE_MASK 0x3
|
||||
#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
|
||||
#define SYSCFG0_SGMII_MASK (3 << 8)
|
||||
#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8))
|
||||
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8))
|
||||
#define SYSCFG0_SGMII_GMAC2_V2 ((1 << 8) & GENMASK(9, 8))
|
||||
#define SYSCFG0_SGMII_MASK GENMASK(9, 8)
|
||||
#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
|
||||
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
|
||||
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
|
||||
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
|
||||
|
||||
|
||||
/* ethernet subsystem clock register */
|
||||
#define ETHSYS_CLKCFG0 0x2c
|
||||
@ -404,6 +406,11 @@
|
||||
#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
|
||||
#define SGMII_PHYA_PWD BIT(4)
|
||||
|
||||
/* Infrasys subsystem config registers */
|
||||
#define INFRA_MISC2 0x70c
|
||||
#define CO_QPHY_SEL BIT(0)
|
||||
#define GEPHY_MAC_SEL BIT(1)
|
||||
|
||||
struct mtk_rx_dma {
|
||||
unsigned int rxd1;
|
||||
unsigned int rxd2;
|
||||
@ -565,19 +572,101 @@ struct mtk_rx_ring {
|
||||
u32 crx_idx_reg;
|
||||
};
|
||||
|
||||
#define MTK_TRGMII BIT(0)
|
||||
#define MTK_GMAC1_TRGMII (BIT(1) | MTK_TRGMII)
|
||||
#define MTK_ESW BIT(4)
|
||||
#define MTK_GMAC1_ESW (BIT(5) | MTK_ESW)
|
||||
#define MTK_SGMII BIT(8)
|
||||
#define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII)
|
||||
#define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII)
|
||||
#define MTK_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \
|
||||
MTK_GMAC2_SGMII)
|
||||
#define MTK_HWLRO BIT(12)
|
||||
#define MTK_SHARED_INT BIT(13)
|
||||
enum mtk_eth_mux {
|
||||
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW,
|
||||
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY,
|
||||
MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
|
||||
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
|
||||
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
|
||||
MTK_ETH_MUX_MAX,
|
||||
};
|
||||
|
||||
enum mtk_eth_path {
|
||||
MTK_ETH_PATH_GMAC1_RGMII,
|
||||
MTK_ETH_PATH_GMAC1_TRGMII,
|
||||
MTK_ETH_PATH_GMAC1_SGMII,
|
||||
MTK_ETH_PATH_GMAC2_RGMII,
|
||||
MTK_ETH_PATH_GMAC2_SGMII,
|
||||
MTK_ETH_PATH_GMAC2_GEPHY,
|
||||
MTK_ETH_PATH_GDM1_ESW,
|
||||
MTK_ETH_PATH_MAX,
|
||||
};
|
||||
|
||||
/* Supported hardware group on SoCs */
|
||||
#define MTK_RGMII BIT(0)
|
||||
#define MTK_TRGMII BIT(1)
|
||||
#define MTK_SGMII BIT(2)
|
||||
#define MTK_ESW BIT(3)
|
||||
#define MTK_GEPHY BIT(4)
|
||||
#define MTK_MUX BIT(5)
|
||||
#define MTK_INFRA BIT(6)
|
||||
#define MTK_SHARED_SGMII BIT(7)
|
||||
#define MTK_HWLRO BIT(8)
|
||||
#define MTK_SHARED_INT BIT(9)
|
||||
|
||||
/* Supported path present on SoCs */
|
||||
#define MTK_PATH_BIT(x) BIT((x) + 10)
|
||||
|
||||
#define MTK_GMAC1_RGMII \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_RGMII) | MTK_RGMII)
|
||||
|
||||
#define MTK_GMAC1_TRGMII \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_TRGMII) | MTK_TRGMII)
|
||||
|
||||
#define MTK_GMAC1_SGMII \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_SGMII) | MTK_SGMII)
|
||||
|
||||
#define MTK_GMAC2_RGMII \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_RGMII) | MTK_RGMII)
|
||||
|
||||
#define MTK_GMAC2_SGMII \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_SGMII) | MTK_SGMII)
|
||||
|
||||
#define MTK_GMAC2_GEPHY \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_GEPHY) | MTK_GEPHY)
|
||||
|
||||
#define MTK_GDM1_ESW \
|
||||
(MTK_PATH_BIT(MTK_ETH_PATH_GDM1_ESW) | MTK_ESW)
|
||||
|
||||
#define MTK_MUX_BIT(x) BIT((x) + 20)
|
||||
|
||||
/* MUXes present on SoCs */
|
||||
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
|
||||
#define MTK_MUX_GDM1_TO_GMAC1_ESW \
|
||||
(MTK_MUX_BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW) | MTK_MUX)
|
||||
|
||||
/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
|
||||
#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
|
||||
(MTK_MUX_BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY) | MTK_MUX | MTK_INFRA)
|
||||
|
||||
/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
|
||||
#define MTK_MUX_U3_GMAC2_TO_QPHY \
|
||||
(MTK_MUX_BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY) | MTK_MUX | MTK_INFRA)
|
||||
|
||||
/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
|
||||
#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
|
||||
(MTK_MUX_BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII) | MTK_MUX | \
|
||||
MTK_SHARED_SGMII)
|
||||
|
||||
/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
|
||||
#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
|
||||
(MTK_MUX_BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII) | MTK_MUX)
|
||||
|
||||
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
|
||||
|
||||
#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
|
||||
MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
|
||||
MTK_MUX_GDM1_TO_GMAC1_ESW | \
|
||||
MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII)
|
||||
|
||||
#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII)
|
||||
|
||||
#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
|
||||
MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
|
||||
MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
|
||||
MTK_MUX_U3_GMAC2_TO_QPHY | \
|
||||
MTK_MUX_GMAC12_TO_GEPHY_SGMII)
|
||||
|
||||
/* struct mtk_eth_data - This is the structure holding all differences
|
||||
* among various plaforms
|
||||
* @ana_rgc3: The offset for register ANA_RGC3 related to
|
||||
@ -633,6 +722,8 @@ struct mtk_sgmii {
|
||||
* @msg_enable: Ethtool msg level
|
||||
* @ethsys: The register map pointing at the range used to setup
|
||||
* MII modes
|
||||
* @infra: The register map pointing at the range used to setup
|
||||
* SGMII and GePHY path
|
||||
* @pctl: The register map pointing at the range used to setup
|
||||
* GMAC port drive/slew values
|
||||
* @dma_refcnt: track how many netdevs are using the DMA engine
|
||||
@ -664,6 +755,7 @@ struct mtk_eth {
|
||||
u32 msg_enable;
|
||||
unsigned long sysclk;
|
||||
struct regmap *ethsys;
|
||||
struct regmap *infra;
|
||||
struct mtk_sgmii *sgmii;
|
||||
struct regmap *pctl;
|
||||
bool hwlro;
|
||||
@ -719,5 +811,6 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
|
||||
u32 ana_rgc3);
|
||||
int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
|
||||
int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id);
|
||||
int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode);
|
||||
|
||||
#endif /* MTK_ETH_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user