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drm/amdgpu: add workaround for issue in DPG for VCN3.0
To workaround an issue in DPG V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1340,6 +1340,10 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
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{
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_device *adev = ring->adev;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
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lower_32_bits(ring->wptr) | 0x80000000);
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if (ring->use_doorbell) {
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if (ring->use_doorbell) {
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adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
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WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
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