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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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OMAP3: hwmod data: Add GPIO
Add GPIO hwmod data for OMAP3 Also remove "omap34xx.h" header file as it is not required anymore. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Varadarajan, Charulatha
Tony Lindgren
parent
aeac0e4410
commit
70034d38fb
@ -20,7 +20,7 @@
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#include <plat/serial.h>
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#include <plat/l4_3xxx.h>
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#include <plat/i2c.h>
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#include <plat/omap34xx.h>
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#include <plat/gpio.h>
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#include "omap_hwmod_common_data.h"
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@ -45,6 +45,12 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
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static struct omap_hwmod omap3xxx_i2c1_hwmod;
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static struct omap_hwmod omap3xxx_i2c2_hwmod;
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static struct omap_hwmod omap3xxx_i2c3_hwmod;
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static struct omap_hwmod omap3xxx_gpio1_hwmod;
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static struct omap_hwmod omap3xxx_gpio2_hwmod;
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static struct omap_hwmod omap3xxx_gpio3_hwmod;
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static struct omap_hwmod omap3xxx_gpio4_hwmod;
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static struct omap_hwmod omap3xxx_gpio5_hwmod;
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static struct omap_hwmod omap3xxx_gpio6_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
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@ -739,6 +745,351 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* l4_wkup -> gpio1 */
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static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
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{
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.pa_start = 0x48310000,
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.pa_end = 0x483101ff,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
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.master = &omap3xxx_l4_wkup_hwmod,
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.slave = &omap3xxx_gpio1_hwmod,
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.addr = omap3xxx_gpio1_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio2 */
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static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
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{
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.pa_start = 0x49050000,
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.pa_end = 0x490501ff,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_gpio2_hwmod,
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.addr = omap3xxx_gpio2_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio3 */
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static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
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{
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.pa_start = 0x49052000,
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.pa_end = 0x490521ff,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_gpio3_hwmod,
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.addr = omap3xxx_gpio3_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio4 */
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static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
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{
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.pa_start = 0x49054000,
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.pa_end = 0x490541ff,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_gpio4_hwmod,
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.addr = omap3xxx_gpio4_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio5 */
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static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
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{
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.pa_start = 0x49056000,
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.pa_end = 0x490561ff,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_gpio5_hwmod,
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.addr = omap3xxx_gpio5_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio6 */
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static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
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{
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.pa_start = 0x49058000,
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.pa_end = 0x490581ff,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_gpio6_hwmod,
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.addr = omap3xxx_gpio6_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/*
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* 'gpio' class
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* general purpose io module
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*/
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static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
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.name = "gpio",
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.sysc = &omap3xxx_gpio_sysc,
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.rev = 1,
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};
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/* gpio_dev_attr*/
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static struct omap_gpio_dev_attr gpio_dev_attr = {
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.bank_width = 32,
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.dbck_flag = true,
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};
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/* gpio1 */
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static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
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{ .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
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};
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static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio1_dbck", },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
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&omap3xxx_l4_wkup__gpio1,
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};
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static struct omap_hwmod omap3xxx_gpio1_hwmod = {
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.name = "gpio1",
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.mpu_irqs = omap3xxx_gpio1_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
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.main_clk = "gpio1_ick",
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.opt_clks = gpio1_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_GPIO1_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
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},
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},
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.slaves = omap3xxx_gpio1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
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.class = &omap3xxx_gpio_hwmod_class,
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.dev_attr = &gpio_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* gpio2 */
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static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
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{ .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
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};
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static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio2_dbck", },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
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&omap3xxx_l4_per__gpio2,
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};
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static struct omap_hwmod omap3xxx_gpio2_hwmod = {
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.name = "gpio2",
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.mpu_irqs = omap3xxx_gpio2_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
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.main_clk = "gpio2_ick",
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.opt_clks = gpio2_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_GPIO2_SHIFT,
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.module_offs = OMAP3430_PER_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
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},
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},
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.slaves = omap3xxx_gpio2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
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.class = &omap3xxx_gpio_hwmod_class,
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.dev_attr = &gpio_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* gpio3 */
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static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
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{ .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
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};
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static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio3_dbck", },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
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&omap3xxx_l4_per__gpio3,
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};
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static struct omap_hwmod omap3xxx_gpio3_hwmod = {
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.name = "gpio3",
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.mpu_irqs = omap3xxx_gpio3_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
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.main_clk = "gpio3_ick",
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.opt_clks = gpio3_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_GPIO3_SHIFT,
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.module_offs = OMAP3430_PER_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
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},
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},
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.slaves = omap3xxx_gpio3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
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.class = &omap3xxx_gpio_hwmod_class,
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.dev_attr = &gpio_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* gpio4 */
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static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
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{ .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
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};
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static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio4_dbck", },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
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&omap3xxx_l4_per__gpio4,
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};
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static struct omap_hwmod omap3xxx_gpio4_hwmod = {
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.name = "gpio4",
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.mpu_irqs = omap3xxx_gpio4_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
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.main_clk = "gpio4_ick",
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.opt_clks = gpio4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_GPIO4_SHIFT,
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.module_offs = OMAP3430_PER_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
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},
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},
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.slaves = omap3xxx_gpio4_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
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.class = &omap3xxx_gpio_hwmod_class,
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.dev_attr = &gpio_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* gpio5 */
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static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
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{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
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};
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static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio5_dbck", },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
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&omap3xxx_l4_per__gpio5,
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};
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static struct omap_hwmod omap3xxx_gpio5_hwmod = {
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.name = "gpio5",
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.mpu_irqs = omap3xxx_gpio5_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
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.main_clk = "gpio5_ick",
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.opt_clks = gpio5_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_GPIO5_SHIFT,
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.module_offs = OMAP3430_PER_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
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},
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},
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.slaves = omap3xxx_gpio5_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
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.class = &omap3xxx_gpio_hwmod_class,
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.dev_attr = &gpio_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* gpio6 */
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static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
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{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
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};
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static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio6_dbck", },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
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&omap3xxx_l4_per__gpio6,
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};
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static struct omap_hwmod omap3xxx_gpio6_hwmod = {
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.name = "gpio6",
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.mpu_irqs = omap3xxx_gpio6_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
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.main_clk = "gpio6_ick",
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.opt_clks = gpio6_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_GPIO6_SHIFT,
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.module_offs = OMAP3430_PER_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
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},
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},
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.slaves = omap3xxx_gpio6_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
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.class = &omap3xxx_gpio_hwmod_class,
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.dev_attr = &gpio_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
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&omap3xxx_l3_main_hwmod,
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&omap3xxx_l4_core_hwmod,
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@ -754,6 +1105,14 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
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&omap3xxx_i2c1_hwmod,
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&omap3xxx_i2c2_hwmod,
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&omap3xxx_i2c3_hwmod,
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/* gpio class */
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&omap3xxx_gpio1_hwmod,
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&omap3xxx_gpio2_hwmod,
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&omap3xxx_gpio3_hwmod,
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&omap3xxx_gpio4_hwmod,
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&omap3xxx_gpio5_hwmod,
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&omap3xxx_gpio6_hwmod,
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NULL,
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};
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