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drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
The revision id range for this workaround has changed. So apply
it to all revids on all gen9.
References: HSD#2134449
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-6-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 5b0e365929
)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
This commit is contained in:
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@ -913,7 +913,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
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{
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struct drm_device *dev = engine->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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int ret;
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/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
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@ -973,12 +972,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
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WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
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PIXEL_MASK_CAMMING_DISABLE);
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/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
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tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
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if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
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IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
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tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
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WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
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/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
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WA_SET_BIT_MASKED(HDC_CHICKEN0,
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HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
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HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
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/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
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if (IS_SKYLAKE(dev_priv) ||
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