mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 01:46:48 +07:00
cxgb4: collect hardware misc dumps
Collect path mtu, PM stats, TP clock info, congestion control, and VPD data dumps. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rahul Lakkireddy
David S. Miller
parent
08c4901bfe
commit
6f92a6544f
@ -49,6 +49,13 @@ struct cudbg_rss_vf_conf {
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u32 rss_vf_vfh;
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};
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struct cudbg_pm_stats {
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u32 tx_cnt[T6_PM_NSTATS];
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u32 rx_cnt[T6_PM_NSTATS];
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u64 tx_cyc[T6_PM_NSTATS];
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u64 rx_cyc[T6_PM_NSTATS];
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};
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struct cudbg_hw_sched {
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u32 kbps[NTX_SCHED];
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u32 ipg[NTX_SCHED];
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@ -85,6 +92,22 @@ struct cudbg_cim_pif_la {
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u8 data[0];
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};
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struct cudbg_clk_info {
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u64 retransmit_min;
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u64 retransmit_max;
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u64 persist_timer_min;
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u64 persist_timer_max;
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u64 keepalive_idle_timer;
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u64 keepalive_interval;
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u64 initial_srtt;
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u64 finwait2_timer;
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u32 dack_timer;
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u32 res;
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u32 cclk_ps;
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u32 tre;
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u32 dack_re;
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};
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struct cudbg_tid_info_region {
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u32 ntids;
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u32 nstids;
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@ -143,6 +166,19 @@ struct cudbg_mps_tcam {
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u8 reserved[2];
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};
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struct cudbg_vpd_data {
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u8 sn[SERNUM_LEN + 1];
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u8 bn[PN_LEN + 1];
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u8 na[MACADDR_LEN + 1];
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u8 mn[ID_LEN + 1];
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u16 fw_major;
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u16 fw_minor;
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u16 fw_micro;
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u16 fw_build;
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u32 scfg_vers;
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u32 vpd_vers;
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};
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#define CUDBG_NUM_ULPTX 11
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#define CUDBG_NUM_ULPTX_READ 512
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@ -49,18 +49,23 @@ enum cudbg_dbg_entity_type {
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CUDBG_EDC1 = 19,
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CUDBG_RSS = 22,
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CUDBG_RSS_VF_CONF = 25,
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CUDBG_PATH_MTU = 27,
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CUDBG_PM_STATS = 30,
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CUDBG_HW_SCHED = 31,
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CUDBG_TP_INDIRECT = 36,
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CUDBG_SGE_INDIRECT = 37,
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CUDBG_ULPRX_LA = 41,
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CUDBG_TP_LA = 43,
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CUDBG_CIM_PIF_LA = 45,
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CUDBG_CLK = 46,
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CUDBG_CIM_OBQ_RXQ0 = 47,
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CUDBG_CIM_OBQ_RXQ1 = 48,
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CUDBG_PCIE_INDIRECT = 50,
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CUDBG_PM_INDIRECT = 51,
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CUDBG_TID_INFO = 54,
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CUDBG_MPS_TCAM = 57,
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CUDBG_VPD_DATA = 58,
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CUDBG_CCTRL = 60,
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CUDBG_MA_INDIRECT = 61,
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CUDBG_ULPTX_LA = 62,
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CUDBG_UP_CIM_INDIRECT = 64,
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@ -574,6 +574,44 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
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return rc;
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}
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int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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int rc;
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rc = cudbg_get_buff(dbg_buff, NMTUS * sizeof(u16), &temp_buff);
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if (rc)
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return rc;
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t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
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cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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return rc;
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}
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int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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struct cudbg_pm_stats *pm_stats_buff;
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int rc;
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rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pm_stats),
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&temp_buff);
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if (rc)
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return rc;
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pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
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t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
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t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
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cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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return rc;
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}
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int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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@ -813,6 +851,55 @@ int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
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return rc;
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}
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int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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struct cudbg_clk_info *clk_info_buff;
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u64 tp_tick_us;
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int rc;
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if (!padap->params.vpd.cclk)
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return CUDBG_STATUS_CCLK_NOT_DEFINED;
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rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_clk_info),
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&temp_buff);
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if (rc)
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return rc;
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clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
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clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
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clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
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clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
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clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
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tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
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clk_info_buff->dack_timer =
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(clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
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t4_read_reg(padap, TP_DACK_TIMER_A);
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clk_info_buff->retransmit_min =
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tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
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clk_info_buff->retransmit_max =
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tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
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clk_info_buff->persist_timer_min =
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tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
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clk_info_buff->persist_timer_max =
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tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
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clk_info_buff->keepalive_idle_timer =
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tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
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clk_info_buff->keepalive_interval =
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tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
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clk_info_buff->initial_srtt =
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tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
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clk_info_buff->finwait2_timer =
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tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
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cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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return rc;
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}
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int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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@ -1196,6 +1283,54 @@ int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
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return rc;
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}
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int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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struct cudbg_vpd_data *vpd_data;
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int rc;
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rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_vpd_data),
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&temp_buff);
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if (rc)
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return rc;
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vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
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memcpy(vpd_data->sn, padap->params.vpd.sn, SERNUM_LEN + 1);
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memcpy(vpd_data->bn, padap->params.vpd.pn, PN_LEN + 1);
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memcpy(vpd_data->na, padap->params.vpd.na, MACADDR_LEN + 1);
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memcpy(vpd_data->mn, padap->params.vpd.id, ID_LEN + 1);
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vpd_data->scfg_vers = padap->params.scfg_vers;
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vpd_data->vpd_vers = padap->params.vpd_vers;
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vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(padap->params.fw_vers);
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vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(padap->params.fw_vers);
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vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(padap->params.fw_vers);
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vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(padap->params.fw_vers);
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cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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return rc;
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}
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int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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u32 size;
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int rc;
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size = sizeof(u16) * NMTUS * NCCTRL_WIN;
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rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
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if (rc)
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return rc;
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t4_read_cong_tbl(padap, (void *)temp_buff.data);
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cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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return rc;
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}
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int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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@ -84,6 +84,12 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
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int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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@ -99,6 +105,9 @@ int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
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int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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@ -117,6 +126,12 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init,
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int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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@ -46,18 +46,23 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
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{ CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi },
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{ CUDBG_RSS, cudbg_collect_rss },
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{ CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config },
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{ CUDBG_PATH_MTU, cudbg_collect_path_mtu },
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{ CUDBG_PM_STATS, cudbg_collect_pm_stats },
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{ CUDBG_HW_SCHED, cudbg_collect_hw_sched },
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{ CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect },
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{ CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect },
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{ CUDBG_ULPRX_LA, cudbg_collect_ulprx_la },
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{ CUDBG_TP_LA, cudbg_collect_tp_la },
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{ CUDBG_CIM_PIF_LA, cudbg_collect_cim_pif_la },
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{ CUDBG_CLK, cudbg_collect_clk_info },
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{ CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 },
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{ CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 },
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{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },
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{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },
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{ CUDBG_TID_INFO, cudbg_collect_tid },
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{ CUDBG_MPS_TCAM, cudbg_collect_mps_tcam },
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{ CUDBG_VPD_DATA, cudbg_collect_vpd_data },
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{ CUDBG_CCTRL, cudbg_collect_cctrl },
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{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },
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{ CUDBG_ULPTX_LA, cudbg_collect_ulptx_la },
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{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
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@ -157,6 +162,12 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
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len = adap->params.arch.vfcount *
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sizeof(struct cudbg_rss_vf_conf);
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break;
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case CUDBG_PATH_MTU:
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len = NMTUS * sizeof(u16);
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break;
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case CUDBG_PM_STATS:
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len = sizeof(struct cudbg_pm_stats);
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break;
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case CUDBG_HW_SCHED:
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len = sizeof(struct cudbg_hw_sched);
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break;
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@ -191,6 +202,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
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len = sizeof(struct cudbg_cim_pif_la);
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len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
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break;
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case CUDBG_CLK:
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len = sizeof(struct cudbg_clk_info);
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break;
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case CUDBG_PCIE_INDIRECT:
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n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
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len = sizeof(struct ireg_buf) * n * 2;
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@ -206,6 +220,12 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
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len = sizeof(struct cudbg_mps_tcam) *
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adap->params.arch.mps_tcam_size;
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break;
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case CUDBG_VPD_DATA:
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len = sizeof(struct cudbg_vpd_data);
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break;
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case CUDBG_CCTRL:
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len = sizeof(u16) * NMTUS * NCCTRL_WIN;
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break;
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case CUDBG_MA_INDIRECT:
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if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
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n = sizeof(t6_ma_ireg_array) /
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