mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 06:56:46 +07:00
Merge branch 'imx/cleanup' into next/cleanup
This commit is contained in:
commit
6f6184a9d0
@ -8,9 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
|
||||
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
|
||||
obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
|
||||
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
|
||||
|
||||
# Support for CMOS sensor interface
|
||||
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
|
||||
|
@ -1,56 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2010 Pengutronix
|
||||
* Sascha Hauer <s.hauer@pengutronix.de>
|
||||
* Juergen Beisert <j.beisert@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static int mxc_init_l2x0(void)
|
||||
{
|
||||
void __iomem *l2x0_base;
|
||||
void __iomem *clkctl_base;
|
||||
|
||||
if (!cpu_is_mx31() && !cpu_is_mx35())
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* First of all, we must repair broken chip settings. There are some
|
||||
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
|
||||
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
|
||||
* Workaraound is to setup the correct register setting prior enabling the
|
||||
* L2 cache. This should not hurt already working CPUs, as they are using the
|
||||
* same value.
|
||||
*/
|
||||
#define L2_MEM_VAL 0x10
|
||||
|
||||
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
|
||||
if (clkctl_base != NULL) {
|
||||
writel(0x00000515, clkctl_base + L2_MEM_VAL);
|
||||
iounmap(clkctl_base);
|
||||
} else {
|
||||
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
|
||||
}
|
||||
|
||||
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
|
||||
if (IS_ERR(l2x0_base)) {
|
||||
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
|
||||
PTR_ERR(l2x0_base));
|
||||
return 0;
|
||||
}
|
||||
|
||||
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(mxc_init_l2x0);
|
256
arch/arm/mach-imx/mm-imx3.c
Normal file
256
arch/arm/mach-imx/mm-imx3.c
Normal file
@ -0,0 +1,256 @@
|
||||
/*
|
||||
* Copyright (C) 1999,2000 Arm Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
|
||||
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* - add MX31 specific definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
static void imx3_idle(void)
|
||||
{
|
||||
unsigned long reg = 0;
|
||||
__asm__ __volatile__(
|
||||
/* disable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"bic %0, %0, #0x00001000\n"
|
||||
"bic %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
/* invalidate I cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c5, 0\n"
|
||||
/* clear and invalidate D cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c14, 0\n"
|
||||
/* WFI */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c0, 4\n"
|
||||
"nop\n" "nop\n" "nop\n" "nop\n"
|
||||
"nop\n" "nop\n" "nop\n"
|
||||
/* enable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"orr %0, %0, #0x00001000\n"
|
||||
"orr %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=r" (reg));
|
||||
}
|
||||
|
||||
static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
|
||||
unsigned int mtype)
|
||||
{
|
||||
if (mtype == MT_DEVICE) {
|
||||
/*
|
||||
* Access all peripherals below 0x80000000 as nonshared device
|
||||
* on mx3, but leave l2cc alone. Otherwise cache corruptions
|
||||
* can occur.
|
||||
*/
|
||||
if (phys_addr < 0x80000000 &&
|
||||
!addr_in_module(phys_addr, MX3x_L2CC))
|
||||
mtype = MT_DEVICE_NONSHARED;
|
||||
}
|
||||
|
||||
return __arm_ioremap(phys_addr, size, mtype);
|
||||
}
|
||||
|
||||
void imx3_init_l2x0(void)
|
||||
{
|
||||
void __iomem *l2x0_base;
|
||||
void __iomem *clkctl_base;
|
||||
|
||||
/*
|
||||
* First of all, we must repair broken chip settings. There are some
|
||||
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
|
||||
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
|
||||
* Workaraound is to setup the correct register setting prior enabling the
|
||||
* L2 cache. This should not hurt already working CPUs, as they are using the
|
||||
* same value.
|
||||
*/
|
||||
#define L2_MEM_VAL 0x10
|
||||
|
||||
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
|
||||
if (clkctl_base != NULL) {
|
||||
writel(0x00000515, clkctl_base + L2_MEM_VAL);
|
||||
iounmap(clkctl_base);
|
||||
} else {
|
||||
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
|
||||
}
|
||||
|
||||
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
|
||||
if (IS_ERR(l2x0_base)) {
|
||||
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
|
||||
PTR_ERR(l2x0_base));
|
||||
return;
|
||||
}
|
||||
|
||||
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
|
||||
}
|
||||
|
||||
static struct map_desc mx31_io_desc[] __initdata = {
|
||||
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
|
||||
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
|
||||
};
|
||||
|
||||
/*
|
||||
* This function initializes the memory map. It is called during the
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx31_map_io(void)
|
||||
{
|
||||
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
|
||||
}
|
||||
|
||||
static struct map_desc mx35_io_desc[] __initdata = {
|
||||
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
|
||||
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
|
||||
};
|
||||
|
||||
void __init mx35_map_io(void)
|
||||
{
|
||||
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
|
||||
}
|
||||
|
||||
void __init imx31_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX31);
|
||||
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
|
||||
imx_idle = imx3_idle;
|
||||
imx_ioremap = imx3_ioremap;
|
||||
}
|
||||
|
||||
void __init imx35_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX35);
|
||||
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
|
||||
imx_idle = imx3_idle;
|
||||
imx_ioremap = imx3_ioremap;
|
||||
}
|
||||
|
||||
void __init mx31_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx35_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
|
||||
.per_2_per_addr = 1677,
|
||||
};
|
||||
|
||||
static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
|
||||
.ap_2_ap_addr = 423,
|
||||
.ap_2_bp_addr = 829,
|
||||
.bp_2_ap_addr = 1029,
|
||||
};
|
||||
|
||||
static struct sdma_platform_data imx31_sdma_pdata __initdata = {
|
||||
.fw_name = "sdma-imx31-to2.bin",
|
||||
.script_addrs = &imx31_to2_sdma_script,
|
||||
};
|
||||
|
||||
void __init imx31_soc_init(void)
|
||||
{
|
||||
int to_version = mx31_revision() >> 4;
|
||||
|
||||
imx3_init_l2x0();
|
||||
|
||||
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
|
||||
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
|
||||
|
||||
if (to_version == 1) {
|
||||
strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
|
||||
strlen(imx31_sdma_pdata.fw_name));
|
||||
imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
|
||||
}
|
||||
|
||||
imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
|
||||
}
|
||||
|
||||
static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
|
||||
.ap_2_ap_addr = 642,
|
||||
.uart_2_mcu_addr = 817,
|
||||
.mcu_2_app_addr = 747,
|
||||
.uartsh_2_mcu_addr = 1183,
|
||||
.per_2_shp_addr = 1033,
|
||||
.mcu_2_shp_addr = 961,
|
||||
.ata_2_mcu_addr = 1333,
|
||||
.mcu_2_ata_addr = 1252,
|
||||
.app_2_mcu_addr = 683,
|
||||
.shp_2_per_addr = 1111,
|
||||
.shp_2_mcu_addr = 892,
|
||||
};
|
||||
|
||||
static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
|
||||
.ap_2_ap_addr = 729,
|
||||
.uart_2_mcu_addr = 904,
|
||||
.per_2_app_addr = 1597,
|
||||
.mcu_2_app_addr = 834,
|
||||
.uartsh_2_mcu_addr = 1270,
|
||||
.per_2_shp_addr = 1120,
|
||||
.mcu_2_shp_addr = 1048,
|
||||
.ata_2_mcu_addr = 1429,
|
||||
.mcu_2_ata_addr = 1339,
|
||||
.app_2_per_addr = 1531,
|
||||
.app_2_mcu_addr = 770,
|
||||
.shp_2_per_addr = 1198,
|
||||
.shp_2_mcu_addr = 979,
|
||||
};
|
||||
|
||||
static struct sdma_platform_data imx35_sdma_pdata __initdata = {
|
||||
.fw_name = "sdma-imx35-to2.bin",
|
||||
.script_addrs = &imx35_to2_sdma_script,
|
||||
};
|
||||
|
||||
void __init imx35_soc_init(void)
|
||||
{
|
||||
int to_version = mx35_revision() >> 4;
|
||||
|
||||
imx3_init_l2x0();
|
||||
|
||||
/* i.mx35 has the i.mx31 type gpio */
|
||||
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
|
||||
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
|
||||
|
||||
if (to_version == 1) {
|
||||
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
|
||||
strlen(imx35_sdma_pdata.fw_name));
|
||||
imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
|
||||
}
|
||||
|
||||
imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
|
||||
}
|
@ -1,91 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 1999,2000 Arm Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
|
||||
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* - add MX31 specific definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
static struct map_desc mx31_io_desc[] __initdata = {
|
||||
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
|
||||
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
|
||||
};
|
||||
|
||||
/*
|
||||
* This function initializes the memory map. It is called during the
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx31_map_io(void)
|
||||
{
|
||||
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
|
||||
}
|
||||
|
||||
void __init imx31_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX31);
|
||||
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx31_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
|
||||
.per_2_per_addr = 1677,
|
||||
};
|
||||
|
||||
static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
|
||||
.ap_2_ap_addr = 423,
|
||||
.ap_2_bp_addr = 829,
|
||||
.bp_2_ap_addr = 1029,
|
||||
};
|
||||
|
||||
static struct sdma_platform_data imx31_sdma_pdata __initdata = {
|
||||
.fw_name = "sdma-imx31-to2.bin",
|
||||
.script_addrs = &imx31_to2_sdma_script,
|
||||
};
|
||||
|
||||
void __init imx31_soc_init(void)
|
||||
{
|
||||
int to_version = mx31_revision() >> 4;
|
||||
|
||||
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
|
||||
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
|
||||
|
||||
if (to_version == 1) {
|
||||
strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
|
||||
strlen(imx31_sdma_pdata.fw_name));
|
||||
imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
|
||||
}
|
||||
|
||||
imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
|
||||
}
|
@ -1,109 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 1999,2000 Arm Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
|
||||
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* - add MX31 specific definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
static struct map_desc mx35_io_desc[] __initdata = {
|
||||
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
|
||||
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
|
||||
};
|
||||
|
||||
void __init mx35_map_io(void)
|
||||
{
|
||||
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
|
||||
}
|
||||
|
||||
void __init imx35_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX35);
|
||||
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx35_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
|
||||
.ap_2_ap_addr = 642,
|
||||
.uart_2_mcu_addr = 817,
|
||||
.mcu_2_app_addr = 747,
|
||||
.uartsh_2_mcu_addr = 1183,
|
||||
.per_2_shp_addr = 1033,
|
||||
.mcu_2_shp_addr = 961,
|
||||
.ata_2_mcu_addr = 1333,
|
||||
.mcu_2_ata_addr = 1252,
|
||||
.app_2_mcu_addr = 683,
|
||||
.shp_2_per_addr = 1111,
|
||||
.shp_2_mcu_addr = 892,
|
||||
};
|
||||
|
||||
static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
|
||||
.ap_2_ap_addr = 729,
|
||||
.uart_2_mcu_addr = 904,
|
||||
.per_2_app_addr = 1597,
|
||||
.mcu_2_app_addr = 834,
|
||||
.uartsh_2_mcu_addr = 1270,
|
||||
.per_2_shp_addr = 1120,
|
||||
.mcu_2_shp_addr = 1048,
|
||||
.ata_2_mcu_addr = 1429,
|
||||
.mcu_2_ata_addr = 1339,
|
||||
.app_2_per_addr = 1531,
|
||||
.app_2_mcu_addr = 770,
|
||||
.shp_2_per_addr = 1198,
|
||||
.shp_2_mcu_addr = 979,
|
||||
};
|
||||
|
||||
static struct sdma_platform_data imx35_sdma_pdata __initdata = {
|
||||
.fw_name = "sdma-imx35-to2.bin",
|
||||
.script_addrs = &imx35_to2_sdma_script,
|
||||
};
|
||||
|
||||
void __init imx35_soc_init(void)
|
||||
{
|
||||
int to_version = mx35_revision() >> 4;
|
||||
|
||||
/* i.mx35 has the i.mx31 type gpio */
|
||||
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
|
||||
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
|
||||
|
||||
if (to_version == 1) {
|
||||
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
|
||||
strlen(imx35_sdma_pdata.fw_name));
|
||||
imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
|
||||
}
|
||||
|
||||
imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
|
||||
}
|
@ -11,7 +11,7 @@
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/system.h>
|
||||
#include <mach/mx27.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static int mx27_suspend_enter(suspend_state_t state)
|
||||
{
|
||||
|
@ -4,7 +4,6 @@
|
||||
|
||||
# Object file lists.
|
||||
obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
|
||||
obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm-imx5.o
|
||||
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
|
||||
|
@ -1,72 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Create static mapping between physical to virtual memory.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
* Define the MX50 memory map.
|
||||
*/
|
||||
static struct map_desc mx50_io_desc[] __initdata = {
|
||||
imx_map_entry(MX50, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX50, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX50, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX50, AIPS2, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* This function initializes the memory map. It is called during the
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx50_map_io(void)
|
||||
{
|
||||
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
|
||||
}
|
||||
|
||||
void __init imx50_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX50);
|
||||
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx50_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init imx50_soc_init(void)
|
||||
{
|
||||
/* i.mx50 has the i.mx31 type gpio */
|
||||
mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
|
||||
}
|
@ -21,12 +21,27 @@
|
||||
#include <mach/devices-common.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
|
||||
static void imx5_idle(void)
|
||||
{
|
||||
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the MX50 memory map.
|
||||
*/
|
||||
static struct map_desc mx50_io_desc[] __initdata = {
|
||||
imx_map_entry(MX50, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX50, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX50, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX50, AIPS2, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* Define the MX51 memory map.
|
||||
*/
|
||||
static struct map_desc mx51_io_desc[] __initdata = {
|
||||
imx_map_entry(MX51, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX51, IRAM, MT_DEVICE),
|
||||
imx_map_entry(MX51, DEBUG, MT_DEVICE),
|
||||
imx_map_entry(MX51, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX51, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX51, AIPS2, MT_DEVICE),
|
||||
@ -36,6 +51,7 @@ static struct map_desc mx51_io_desc[] __initdata = {
|
||||
* Define the MX53 memory map.
|
||||
*/
|
||||
static struct map_desc mx53_io_desc[] __initdata = {
|
||||
imx_map_entry(MX53, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX53, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX53, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX53, AIPS2, MT_DEVICE),
|
||||
@ -46,21 +62,34 @@ static struct map_desc mx53_io_desc[] __initdata = {
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx50_map_io(void)
|
||||
{
|
||||
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
|
||||
}
|
||||
|
||||
void __init mx51_map_io(void)
|
||||
{
|
||||
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
|
||||
}
|
||||
|
||||
void __init mx53_map_io(void)
|
||||
{
|
||||
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
|
||||
}
|
||||
|
||||
void __init imx50_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX50);
|
||||
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init imx51_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX51);
|
||||
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx53_map_io(void)
|
||||
{
|
||||
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
|
||||
imx_idle = imx5_idle;
|
||||
}
|
||||
|
||||
void __init imx53_init_early(void)
|
||||
@ -70,35 +99,19 @@ void __init imx53_init_early(void)
|
||||
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx50_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx51_init_irq(void)
|
||||
{
|
||||
unsigned long tzic_addr;
|
||||
void __iomem *tzic_virt;
|
||||
|
||||
if (mx51_revision() < IMX_CHIP_REVISION_2_0)
|
||||
tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
|
||||
else
|
||||
tzic_addr = MX51_TZIC_BASE_ADDR;
|
||||
|
||||
tzic_virt = ioremap(tzic_addr, SZ_16K);
|
||||
if (!tzic_virt)
|
||||
panic("unable to map TZIC interrupt controller\n");
|
||||
|
||||
tzic_init_irq(tzic_virt);
|
||||
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx53_init_irq(void)
|
||||
{
|
||||
unsigned long tzic_addr;
|
||||
void __iomem *tzic_virt;
|
||||
|
||||
tzic_addr = MX53_TZIC_BASE_ADDR;
|
||||
|
||||
tzic_virt = ioremap(tzic_addr, SZ_16K);
|
||||
if (!tzic_virt)
|
||||
panic("unable to map TZIC interrupt controller\n");
|
||||
|
||||
tzic_init_irq(tzic_virt);
|
||||
tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
|
||||
@ -138,6 +151,17 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
|
||||
.script_addrs = &imx53_sdma_script,
|
||||
};
|
||||
|
||||
void __init imx50_soc_init(void)
|
||||
{
|
||||
/* i.mx50 has the i.mx31 type gpio */
|
||||
mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
|
||||
}
|
||||
|
||||
void __init imx51_soc_init(void)
|
||||
{
|
||||
/* i.mx51 has the i.mx31 type gpio */
|
||||
|
@ -14,7 +14,8 @@
|
||||
#include <linux/err.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <mach/system.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include "crm_regs.h"
|
||||
|
||||
static struct clk *gpc_dvfs_clk;
|
||||
|
@ -13,6 +13,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include "crm_regs.h"
|
||||
|
||||
/* set cpu low power mode before WFI instruction. This function is called
|
||||
|
@ -1,11 +1,11 @@
|
||||
# Common support
|
||||
obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o
|
||||
obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
|
||||
|
||||
obj-$(CONFIG_MXS_OCOTP) += ocotp.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
|
||||
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
|
||||
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
|
||||
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
|
||||
|
||||
obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
|
||||
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
|
||||
|
@ -351,6 +351,11 @@ static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio mx28evk_lcd_gpios[] = {
|
||||
{ MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
|
||||
{ MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
|
||||
};
|
||||
|
||||
static void __init mx28evk_init(void)
|
||||
{
|
||||
int ret;
|
||||
@ -377,18 +382,11 @@ static void __init mx28evk_init(void)
|
||||
mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
|
||||
}
|
||||
|
||||
ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
|
||||
ret = gpio_request_array(mx28evk_lcd_gpios,
|
||||
ARRAY_SIZE(mx28evk_lcd_gpios));
|
||||
if (ret)
|
||||
pr_warn("failed to request gpio lcd-enable: %d\n", ret);
|
||||
pr_warn("failed to request gpio pins for lcd: %d\n", ret);
|
||||
else
|
||||
gpio_set_value(MX28EVK_LCD_ENABLE, 1);
|
||||
|
||||
ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
|
||||
if (ret)
|
||||
pr_warn("failed to request gpio bl-enable: %d\n", ret);
|
||||
else
|
||||
gpio_set_value(MX28EVK_BL_ENABLE, 1);
|
||||
|
||||
mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
|
||||
|
||||
/* power on mmc slot by writing 0 to the gpio */
|
||||
@ -402,6 +400,7 @@ static void __init mx28evk_init(void)
|
||||
"mmc1-slot-power");
|
||||
if (ret)
|
||||
pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
|
||||
else
|
||||
mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
|
||||
|
||||
gpio_led_register_device(0, &mx28evk_led_data);
|
||||
|
@ -1,44 +0,0 @@
|
||||
/*
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*
|
||||
* Create static mapping between physical to virtual memory.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/mx23.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux.h>
|
||||
|
||||
/*
|
||||
* Define the MX23 memory map.
|
||||
*/
|
||||
static struct map_desc mx23_io_desc[] __initdata = {
|
||||
mxs_map_entry(MX23, OCRAM, MT_DEVICE),
|
||||
mxs_map_entry(MX23, IO, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* This function initializes the memory map. It is called during the
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx23_map_io(void)
|
||||
{
|
||||
iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
|
||||
}
|
||||
|
||||
void __init mx23_init_irq(void)
|
||||
{
|
||||
icoll_init_irq();
|
||||
}
|
@ -16,10 +16,19 @@
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/mx23.h>
|
||||
#include <mach/mx28.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux.h>
|
||||
|
||||
/*
|
||||
* Define the MX23 memory map.
|
||||
*/
|
||||
static struct map_desc mx23_io_desc[] __initdata = {
|
||||
mxs_map_entry(MX23, OCRAM, MT_DEVICE),
|
||||
mxs_map_entry(MX23, IO, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* Define the MX28 memory map.
|
||||
*/
|
||||
@ -33,6 +42,16 @@ static struct map_desc mx28_io_desc[] __initdata = {
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx23_map_io(void)
|
||||
{
|
||||
iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
|
||||
}
|
||||
|
||||
void __init mx23_init_irq(void)
|
||||
{
|
||||
icoll_init_irq();
|
||||
}
|
||||
|
||||
void __init mx28_map_io(void)
|
||||
{
|
||||
iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
|
@ -71,4 +71,15 @@ extern void mxc_arch_reset_init(void __iomem *);
|
||||
extern void mx51_efikamx_reset(void);
|
||||
extern int mx53_revision(void);
|
||||
extern int mx53_display_revision(void);
|
||||
|
||||
enum mxc_cpu_pwr_mode {
|
||||
WAIT_CLOCKED, /* wfi only */
|
||||
WAIT_UNCLOCKED, /* WAIT */
|
||||
WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
|
||||
STOP_POWER_ON, /* just STOP */
|
||||
STOP_POWER_OFF, /* STOP + SRPG */
|
||||
};
|
||||
|
||||
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
|
||||
extern void (*imx_idle)(void);
|
||||
#endif
|
||||
|
@ -81,11 +81,16 @@
|
||||
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
|
||||
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
|
||||
* mx51:
|
||||
* TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000
|
||||
* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
|
||||
* DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
|
||||
* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
|
||||
* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
|
||||
* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
|
||||
* mx53:
|
||||
* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
|
||||
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
|
||||
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
|
||||
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
|
||||
*/
|
||||
#define IMX_IO_P2V(x) ( \
|
||||
0xf4000000 + \
|
||||
|
@ -14,32 +14,22 @@
|
||||
/* Allow IO space to be anywhere in the memory */
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define __arch_ioremap __imx_ioremap
|
||||
#define __arch_iounmap __iounmap
|
||||
|
||||
#define addr_in_module(addr, mod) \
|
||||
((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
|
||||
|
||||
extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
|
||||
|
||||
static inline void __iomem *
|
||||
__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
|
||||
{
|
||||
if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
|
||||
/*
|
||||
* Access all peripherals below 0x80000000 as nonshared device
|
||||
* on mx3, but leave l2cc alone. Otherwise cache corruptions
|
||||
* can occur.
|
||||
*/
|
||||
if (phys_addr < 0x80000000 &&
|
||||
!addr_in_module(phys_addr, MX3x_L2CC))
|
||||
mtype = MT_DEVICE_NONSHARED;
|
||||
}
|
||||
|
||||
if (imx_ioremap != NULL)
|
||||
return imx_ioremap(phys_addr, size, mtype);
|
||||
else
|
||||
return __arm_ioremap(phys_addr, size, mtype);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* io address mapping macro */
|
||||
#define __io(a) __typesafe_io(a)
|
||||
|
@ -18,18 +18,6 @@
|
||||
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
|
||||
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
|
||||
|
||||
#define MX51_DEBUG_BASE_ADDR 0x60000000
|
||||
#define MX51_DEBUG_SIZE SZ_1M
|
||||
|
||||
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
|
||||
#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000)
|
||||
#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000)
|
||||
#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000)
|
||||
#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000)
|
||||
#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000)
|
||||
#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000)
|
||||
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000)
|
||||
|
||||
/*
|
||||
* SPBA global module enabled #0
|
||||
*/
|
||||
@ -135,6 +123,7 @@
|
||||
|
||||
#define MX51_GPU2D_BASE_ADDR 0xd0000000
|
||||
#define MX51_TZIC_BASE_ADDR 0xe0000000
|
||||
#define MX51_TZIC_SIZE SZ_16K
|
||||
|
||||
#define MX51_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
|
||||
@ -353,7 +342,4 @@ extern int mx51_revision(void);
|
||||
extern void mx51_display_revision(void);
|
||||
#endif
|
||||
|
||||
/* tape-out 1 defines */
|
||||
#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000
|
||||
|
||||
#endif /* ifndef __MACH_MX51_H__ */
|
||||
|
@ -9,6 +9,7 @@
|
||||
|
||||
/* TZIC */
|
||||
#define MX53_TZIC_BASE_ADDR 0x0FFFC000
|
||||
#define MX53_TZIC_SIZE SZ_16K
|
||||
|
||||
/*
|
||||
* AHCI SATA
|
||||
|
@ -183,13 +183,6 @@ struct cpu_op {
|
||||
};
|
||||
|
||||
int tzic_enable_wake(int is_idle);
|
||||
enum mxc_cpu_pwr_mode {
|
||||
WAIT_CLOCKED, /* wfi only */
|
||||
WAIT_UNCLOCKED, /* WAIT */
|
||||
WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
|
||||
STOP_POWER_ON, /* just STOP */
|
||||
STOP_POWER_OFF, /* STOP + SRPG */
|
||||
};
|
||||
|
||||
extern struct cpu_op *(*get_cpu_op)(int *op);
|
||||
#endif
|
||||
|
@ -17,41 +17,12 @@
|
||||
#ifndef __ASM_ARCH_MXC_SYSTEM_H__
|
||||
#define __ASM_ARCH_MXC_SYSTEM_H__
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
|
||||
extern void (*imx_idle)(void);
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
|
||||
if (cpu_is_mx31() || cpu_is_mx35()) {
|
||||
unsigned long reg = 0;
|
||||
__asm__ __volatile__(
|
||||
/* disable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"bic %0, %0, #0x00001000\n"
|
||||
"bic %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
/* invalidate I cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c5, 0\n"
|
||||
/* clear and invalidate D cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c14, 0\n"
|
||||
/* WFI */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c0, 4\n"
|
||||
"nop\n" "nop\n" "nop\n" "nop\n"
|
||||
"nop\n" "nop\n" "nop\n"
|
||||
/* enable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"orr %0, %0, #0x00001000\n"
|
||||
"orr %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=r" (reg));
|
||||
} else if (cpu_is_mx51())
|
||||
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
|
||||
if (imx_idle != NULL)
|
||||
(imx_idle)();
|
||||
else
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
@ -28,6 +28,9 @@
|
||||
#include <asm/system.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
void (*imx_idle)(void) = NULL;
|
||||
void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
|
||||
|
||||
static void __iomem *wdog_base;
|
||||
|
||||
/*
|
||||
|
Loading…
Reference in New Issue
Block a user