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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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can: rcar_canfd: Add Classical CAN only mode support
The controller can operate in one of the two global modes - CAN FD only mode (default) - Classical CAN (CAN2.0) only mode This patch adds support for Classical CAN only mode. It can be enabled by defining the optional device tree property "renesas,no-can-fd" of this node. Note: R-Car Gen3 h/w manual v0.51E shows bit6 of RSCFDnCFDGCFG as reserved, which is incorrect. This bit is same as RSCFDnGCFG. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Ramesh Shanmugasundaram
Marc Kleine-Budde
parent
2781ff5c8f
commit
6f4c2eea35
@ -32,6 +32,12 @@ below properties.
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- assigned-clocks: phandle of canfd clock.
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- assigned-clock-rates: maximum frequency of this clock.
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Optional property:
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The controller can operate in either CAN FD only mode (default) or
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Classical CAN only mode. The mode is global to both the channels. In order to
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enable the later, define the following optional property.
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- renesas,no-can-fd: puts the controller in Classical CAN only mode.
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Example
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-------
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@ -63,12 +69,13 @@ SoC common .dtsi file:
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Board specific .dts file:
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E.g. below enables Channel 1 alone in the board.
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E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
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&canfd {
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pinctrl-0 = <&canfd1_pins>;
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pinctrl-names = "default";
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status = "okay";
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pinctrl-0 = <&canfd1_pins>;
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pinctrl-names = "default";
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renesas,no-can-fd;
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status = "okay";
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channel1 {
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status = "okay";
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@ -79,9 +86,9 @@ E.g. below enables Channel 0 alone in the board using External clock
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as fCAN clock.
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&canfd {
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pinctrl-0 = <&canfd0_pins &can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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pinctrl-0 = <&canfd0_pins &can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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@ -16,8 +16,9 @@
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* mode, the controller acts as a CAN FD node that can also interoperate with
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* CAN 2.0 nodes.
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*
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* As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
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* which is handled by a different register map compared to CAN FD only mode.
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* To switch the controller to Classical CAN (CAN 2.0) only mode, add
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* "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
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* also required to switch modes.
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*
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* Note: The h/w manual register naming convention is clumsy and not acceptable
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* to use as it is in the driver. However, those names are added as comments
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@ -48,15 +49,16 @@
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/* RSCFDnCFDGRMCFG */
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#define RCANFD_GRMCFG_RCMC BIT(0)
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/* RSCFDnCFDGCFG */
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#define RCANFD_GCFG_CMPOC BIT(5)
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/* RSCFDnCFDGCFG / RSCFDnGCFG */
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#define RCANFD_GCFG_EEFE BIT(6)
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#define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */
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#define RCANFD_GCFG_DCS BIT(4)
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#define RCANFD_GCFG_DCE BIT(1)
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#define RCANFD_GCFG_TPRI BIT(0)
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/* RSCFDnCFDGCTR */
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/* RSCFDnCFDGCTR / RSCFDnGCTR */
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#define RCANFD_GCTR_TSRST BIT(16)
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#define RCANFD_GCTR_CFMPOFIE BIT(11)
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#define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */
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#define RCANFD_GCTR_THLEIE BIT(10)
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#define RCANFD_GCTR_MEIE BIT(9)
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#define RCANFD_GCTR_DEIE BIT(8)
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@ -66,7 +68,7 @@
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#define RCANFD_GCTR_GMDC_GRESET (0x1)
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#define RCANFD_GCTR_GMDC_GTEST (0x2)
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/* RSCFDnCFDGSTS */
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/* RSCFDnCFDGSTS / RSCFDnGSTS */
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#define RCANFD_GSTS_GRAMINIT BIT(3)
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#define RCANFD_GSTS_GSLPSTS BIT(2)
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#define RCANFD_GSTS_GHLTSTS BIT(1)
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@ -74,44 +76,50 @@
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/* Non-operational status */
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#define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/* RSCFDnCFDGERFL */
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/* RSCFDnCFDGERFL / RSCFDnGERFL */
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#define RCANFD_GERFL_EEF1 BIT(17)
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#define RCANFD_GERFL_EEF0 BIT(16)
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#define RCANFD_GERFL_CMPOF BIT(3)
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#define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */
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#define RCANFD_GERFL_THLES BIT(2)
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#define RCANFD_GERFL_MES BIT(1)
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#define RCANFD_GERFL_DEF BIT(0)
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#define RCANFD_GERFL_ERR(x) ((x) & (RCANFD_GERFL_EEF1 |\
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RCANFD_GERFL_EEF0 |\
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RCANFD_GERFL_MES |\
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RCANFD_GERFL_CMPOF))
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#define RCANFD_GERFL_ERR(gpriv, x) ((x) & (RCANFD_GERFL_EEF1 |\
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RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
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(gpriv->fdmode ?\
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RCANFD_GERFL_CMPOF : 0)))
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/* AFL Rx rules registers */
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/* RSCFDnCFDGAFLCFG0 */
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/* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
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#define RCANFD_GAFLCFG_SETRNC(n, x) (((x) & 0xff) << (24 - n * 8))
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#define RCANFD_GAFLCFG_GETRNC(n, x) (((x) >> (24 - n * 8)) & 0xff)
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/* RSCFDnCFDGAFLECTR */
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/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
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#define RCANFD_GAFLECTR_AFLDAE BIT(8)
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#define RCANFD_GAFLECTR_AFLPN(x) ((x) & 0x1f)
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/* RSCFDnCFDGAFLIDj */
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/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
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#define RCANFD_GAFLID_GAFLLB BIT(29)
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/* RSCFDnCFDGAFLP1_j */
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/* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
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#define RCANFD_GAFLP1_GAFLFDP(x) (1 << (x))
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/* Channel register bits */
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/* RSCFDnCFDCmNCFG */
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/* RSCFDnCmCFG - Classical CAN only */
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#define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24)
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#define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20)
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#define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16)
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#define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0)
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/* RSCFDnCFDCmNCFG - CAN FD only */
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#define RCANFD_NCFG_NTSEG2(x) (((x) & 0x1f) << 24)
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#define RCANFD_NCFG_NTSEG1(x) (((x) & 0x7f) << 16)
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#define RCANFD_NCFG_NSJW(x) (((x) & 0x1f) << 11)
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#define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
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/* RSCFDnCFDCmCTR */
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/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
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#define RCANFD_CCTR_CTME BIT(24)
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#define RCANFD_CCTR_ERRD BIT(23)
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#define RCANFD_CCTR_BOM_MASK (0x3 << 21)
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@ -136,7 +144,7 @@
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#define RCANFD_CCTR_CHDMC_CRESET (0x1)
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#define RCANFD_CCTR_CHDMC_CHLT (0x2)
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/* RSCFDnCFDCmSTS */
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/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
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#define RCANFD_CSTS_COMSTS BIT(7)
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#define RCANFD_CSTS_RECSTS BIT(6)
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#define RCANFD_CSTS_TRMSTS BIT(5)
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@ -149,7 +157,7 @@
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#define RCANFD_CSTS_TECCNT(x) (((x) >> 24) & 0xff)
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#define RCANFD_CSTS_RECCNT(x) (((x) >> 16) & 0xff)
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/* RSCFDnCFDCmERFL */
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/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
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#define RCANFD_CERFL_ADERR BIT(14)
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#define RCANFD_CERFL_B0ERR BIT(13)
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#define RCANFD_CERFL_B1ERR BIT(12)
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@ -239,14 +247,14 @@
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#define RCANFD_CFFDCSTS_CFBRS BIT(1)
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#define RCANFD_CFFDCSTS_CFESI BIT(0)
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/* This controller supports classical CAN only mode or CAN FD only mode. These
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* modes are supported in two separate set of register maps & names. However,
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* some of the register offsets are common for both modes. Those offsets are
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* listed below as Common registers.
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/* This controller supports either Classical CAN only mode or CAN FD only mode.
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* These modes are supported in two separate set of register maps & names.
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* However, some of the register offsets are common for both modes. Those
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* offsets are listed below as Common registers.
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*
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* The CAN FD only specific registers are listed separately and their names
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* starts with RCANFD_F_xxx names. When classical CAN only specific registers
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* are added, those specific registers can be prefixed as RCANFD_C_xxx.
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* The CAN FD only mode specific registers & Classical CAN only mode specific
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* registers are listed separately. Their register names starts with
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* RCANFD_F_xxx & RCANFD_C_xxx respectively.
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*/
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/* Common registers */
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@ -353,7 +361,7 @@
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#define RCANFD_GTSTCTR (0x046c)
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/* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
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#define RCANFD_GLOCKK (0x047c)
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/* RSCFDnCFDGRMCFG / RSCFDnGRMCFG */
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/* RSCFDnCFDGRMCFG */
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#define RCANFD_GRMCFG (0x04fc)
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/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
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@ -365,6 +373,46 @@
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/* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
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#define RCANFD_GAFLP1(offset, j) ((offset) + 0x0c + (0x10 * (j)))
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/* Classical CAN only mode register map */
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/* RSCFDnGAFLXXXj offset */
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#define RCANFD_C_GAFL_OFFSET (0x0500)
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/* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
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#define RCANFD_C_RMID(q) (0x0600 + (0x10 * (q)))
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#define RCANFD_C_RMPTR(q) (0x0604 + (0x10 * (q)))
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#define RCANFD_C_RMDF0(q) (0x0608 + (0x10 * (q)))
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#define RCANFD_C_RMDF1(q) (0x060c + (0x10 * (q)))
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/* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
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#define RCANFD_C_RFOFFSET (0x0e00)
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#define RCANFD_C_RFID(x) (RCANFD_C_RFOFFSET + (0x10 * (x)))
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#define RCANFD_C_RFPTR(x) (RCANFD_C_RFOFFSET + 0x04 + \
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(0x10 * (x)))
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#define RCANFD_C_RFDF(x, df) (RCANFD_C_RFOFFSET + 0x08 + \
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(0x10 * (x)) + (0x04 * (df)))
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/* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
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#define RCANFD_C_CFOFFSET (0x0e80)
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#define RCANFD_C_CFID(ch, idx) (RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
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(0x10 * (idx)))
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#define RCANFD_C_CFPTR(ch, idx) (RCANFD_C_CFOFFSET + 0x04 + \
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(0x30 * (ch)) + (0x10 * (idx)))
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#define RCANFD_C_CFDF(ch, idx, df) (RCANFD_C_CFOFFSET + 0x08 + \
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(0x30 * (ch)) + (0x10 * (idx)) + \
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(0x04 * (df)))
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/* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
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#define RCANFD_C_TMID(p) (0x1000 + (0x10 * (p)))
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#define RCANFD_C_TMPTR(p) (0x1004 + (0x10 * (p)))
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#define RCANFD_C_TMDF0(p) (0x1008 + (0x10 * (p)))
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#define RCANFD_C_TMDF1(p) (0x100c + (0x10 * (p)))
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/* RSCFDnTHLACCm */
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#define RCANFD_C_THLACC(m) (0x1800 + (0x04 * (m)))
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/* RSCFDnRPGACCr */
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#define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
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/* CAN FD mode specific regsiter map */
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/* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
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@ -468,6 +516,7 @@ struct rcar_canfd_global {
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struct clk *can_clk; /* fCAN clock */
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enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
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unsigned long channels_mask; /* Enabled channels mask */
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bool fdmode; /* CAN FD or Classical CAN only mode */
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};
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/* CAN FD mode nominal rate constants */
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@ -496,6 +545,19 @@ static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
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.brp_inc = 1,
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};
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/* Classical CAN mode bitrate constants */
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static const struct can_bittiming_const rcar_canfd_bittiming_const = {
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.name = RCANFD_DRV_NAME,
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.tseg1_min = 4,
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.tseg1_max = 16,
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.tseg2_min = 2,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 1024,
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.brp_inc = 1,
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};
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/* Helper functions */
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static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
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{
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@ -593,8 +655,13 @@ static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
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/* Reset Global error flags */
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rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
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/* Set the controller into FD mode */
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rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG, RCANFD_GRMCFG_RCMC);
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/* Set the controller into appropriate mode */
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if (gpriv->fdmode)
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rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
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RCANFD_GRMCFG_RCMC);
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else
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rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
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RCANFD_GRMCFG_RCMC);
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/* Transition all Channels to reset mode */
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for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
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@ -624,8 +691,12 @@ static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
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/* Global configuration settings */
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/* Truncate payload to configured message size RFPLS */
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cfg = RCANFD_GCFG_CMPOC;
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/* ECC Error flag Enable */
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cfg = RCANFD_GCFG_EEFE;
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if (gpriv->fdmode)
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/* Truncate payload to configured message size RFPLS */
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cfg |= RCANFD_GCFG_CMPOC;
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/* Set External Clock if selected */
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if (gpriv->fcan != RCANFD_CANFDCLK)
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@ -647,7 +718,7 @@ static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
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u32 ch)
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{
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u32 cfg;
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int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
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int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
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u32 ridx = ch + RCANFD_RFFIFO_IDX;
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if (ch == 0) {
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@ -667,19 +738,19 @@ static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
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/* Write number of rules for channel */
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rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
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RCANFD_GAFLCFG_SETRNC(ch, num_rules));
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if (gpriv->fdmode)
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offset = RCANFD_F_GAFL_OFFSET;
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else
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offset = RCANFD_C_GAFL_OFFSET;
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/* Accept all IDs */
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rcar_canfd_write(gpriv->base,
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RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
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rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
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/* IDE or RTR is not considered for matching */
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rcar_canfd_write(gpriv->base,
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RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
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rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
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/* Any data length accepted */
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rcar_canfd_write(gpriv->base,
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RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
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rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
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/* Place the msg in corresponding Rx FIFO entry */
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rcar_canfd_write(gpriv->base,
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RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
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rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
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RCANFD_GAFLP1_GAFLFDP(ridx));
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/* Disable write access to page */
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@ -697,7 +768,10 @@ static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
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u32 ridx = ch + RCANFD_RFFIFO_IDX;
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rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
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rfpls = 7; /* b111 - Max 64 bytes payload */
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if (gpriv->fdmode)
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rfpls = 7; /* b111 - Max 64 bytes payload */
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else
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rfpls = 0; /* b000 - Max 8 bytes payload */
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cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
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RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
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@ -718,16 +792,20 @@ static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
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cftml = 0; /* 0th buffer */
|
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cfm = 1; /* b01 - Transmit mode */
|
||||
cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
|
||||
cfpls = 7; /* b111 - Max 64 bytes payload */
|
||||
if (gpriv->fdmode)
|
||||
cfpls = 7; /* b111 - Max 64 bytes payload */
|
||||
else
|
||||
cfpls = 0; /* b000 - Max 8 bytes payload */
|
||||
|
||||
cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
|
||||
RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
|
||||
RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
|
||||
rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
|
||||
|
||||
/* Clear FD mode specific control/status register */
|
||||
rcar_canfd_write(gpriv->base,
|
||||
RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
|
||||
if (gpriv->fdmode)
|
||||
/* Clear FD mode specific control/status register */
|
||||
rcar_canfd_write(gpriv->base,
|
||||
RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
|
||||
}
|
||||
|
||||
static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
|
||||
@ -739,7 +817,8 @@ static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
|
||||
|
||||
/* Global interrupts setup */
|
||||
ctr = RCANFD_GCTR_MEIE;
|
||||
ctr |= RCANFD_GCTR_CFMPOFIE;
|
||||
if (gpriv->fdmode)
|
||||
ctr |= RCANFD_GCTR_CFMPOFIE;
|
||||
|
||||
rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
|
||||
}
|
||||
@ -790,6 +869,7 @@ static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
|
||||
static void rcar_canfd_global_error(struct net_device *ndev)
|
||||
{
|
||||
struct rcar_canfd_channel *priv = netdev_priv(ndev);
|
||||
struct rcar_canfd_global *gpriv = priv->gpriv;
|
||||
struct net_device_stats *stats = &ndev->stats;
|
||||
u32 ch = priv->channel;
|
||||
u32 gerfl, sts;
|
||||
@ -823,7 +903,7 @@ static void rcar_canfd_global_error(struct net_device *ndev)
|
||||
sts & ~RCANFD_RFSTS_RFMLT);
|
||||
}
|
||||
}
|
||||
if (gerfl & RCANFD_GERFL_CMPOF) {
|
||||
if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
|
||||
/* Message Lost flag will be set for respective channel
|
||||
* when this condition happens with counters and flags
|
||||
* already updated.
|
||||
@ -1018,7 +1098,7 @@ static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
|
||||
|
||||
/* Global error interrupts */
|
||||
gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
|
||||
if (RCANFD_GERFL_ERR(gerfl))
|
||||
if (RCANFD_GERFL_ERR(gpriv, gerfl))
|
||||
rcar_canfd_global_error(ndev);
|
||||
|
||||
/* Handle Rx interrupts */
|
||||
@ -1077,25 +1157,37 @@ static void rcar_canfd_set_bittiming(struct net_device *dev)
|
||||
tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
|
||||
tseg2 = bt->phase_seg2 - 1;
|
||||
|
||||
cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
|
||||
RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
/* CAN FD only mode */
|
||||
cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
|
||||
RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
|
||||
|
||||
rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
|
||||
netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
|
||||
brp, sjw, tseg1, tseg2);
|
||||
rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
|
||||
netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
|
||||
brp, sjw, tseg1, tseg2);
|
||||
|
||||
/* Data bit timing settings */
|
||||
brp = dbt->brp - 1;
|
||||
sjw = dbt->sjw - 1;
|
||||
tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
|
||||
tseg2 = dbt->phase_seg2 - 1;
|
||||
/* Data bit timing settings */
|
||||
brp = dbt->brp - 1;
|
||||
sjw = dbt->sjw - 1;
|
||||
tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
|
||||
tseg2 = dbt->phase_seg2 - 1;
|
||||
|
||||
cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
|
||||
RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
|
||||
cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
|
||||
RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
|
||||
|
||||
rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
|
||||
netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
|
||||
brp, sjw, tseg1, tseg2);
|
||||
rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
|
||||
netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
|
||||
brp, sjw, tseg1, tseg2);
|
||||
} else {
|
||||
/* Classical CAN only mode */
|
||||
cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
|
||||
RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
|
||||
|
||||
rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
|
||||
netdev_dbg(priv->ndev,
|
||||
"rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
|
||||
brp, sjw, tseg1, tseg2);
|
||||
}
|
||||
}
|
||||
|
||||
static int rcar_canfd_start(struct net_device *ndev)
|
||||
@ -1233,28 +1325,38 @@ static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
|
||||
if (cf->can_id & CAN_RTR_FLAG)
|
||||
id |= RCANFD_CFID_CFRTR;
|
||||
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
|
||||
dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
|
||||
|
||||
if (can_is_canfd_skb(skb)) {
|
||||
/* CAN FD frame format */
|
||||
sts |= RCANFD_CFFDCSTS_CFFDF;
|
||||
if (cf->flags & CANFD_BRS)
|
||||
sts |= RCANFD_CFFDCSTS_CFBRS;
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
|
||||
|
||||
if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
|
||||
sts |= RCANFD_CFFDCSTS_CFESI;
|
||||
if (can_is_canfd_skb(skb)) {
|
||||
/* CAN FD frame format */
|
||||
sts |= RCANFD_CFFDCSTS_CFFDF;
|
||||
if (cf->flags & CANFD_BRS)
|
||||
sts |= RCANFD_CFFDCSTS_CFBRS;
|
||||
|
||||
if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
|
||||
sts |= RCANFD_CFFDCSTS_CFESI;
|
||||
}
|
||||
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
|
||||
|
||||
rcar_canfd_put_data(priv, cf,
|
||||
RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
|
||||
} else {
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
|
||||
rcar_canfd_write(priv->base,
|
||||
RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
|
||||
rcar_canfd_put_data(priv, cf,
|
||||
RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
|
||||
}
|
||||
|
||||
rcar_canfd_write(priv->base, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX),
|
||||
sts);
|
||||
|
||||
rcar_canfd_put_data(priv, cf,
|
||||
RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
|
||||
|
||||
priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
|
||||
can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
|
||||
|
||||
@ -1280,47 +1382,61 @@ static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
|
||||
struct net_device_stats *stats = &priv->ndev->stats;
|
||||
struct canfd_frame *cf;
|
||||
struct sk_buff *skb;
|
||||
u32 sts = 0, id, ptr;
|
||||
u32 sts = 0, id, dlc;
|
||||
u32 ch = priv->channel;
|
||||
u32 ridx = ch + RCANFD_RFFIFO_IDX;
|
||||
|
||||
id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
|
||||
ptr = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
|
||||
dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
|
||||
|
||||
sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
|
||||
if (sts & RCANFD_RFFDSTS_RFFDF)
|
||||
skb = alloc_canfd_skb(priv->ndev, &cf);
|
||||
else
|
||||
skb = alloc_can_skb(priv->ndev,
|
||||
(struct can_frame **)&cf);
|
||||
sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
|
||||
if (sts & RCANFD_RFFDSTS_RFFDF)
|
||||
skb = alloc_canfd_skb(priv->ndev, &cf);
|
||||
else
|
||||
skb = alloc_can_skb(priv->ndev,
|
||||
(struct can_frame **)&cf);
|
||||
} else {
|
||||
id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
|
||||
dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
|
||||
skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
|
||||
}
|
||||
|
||||
if (!skb) {
|
||||
stats->rx_dropped++;
|
||||
return;
|
||||
}
|
||||
|
||||
if (sts & RCANFD_RFFDSTS_RFFDF)
|
||||
cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(ptr));
|
||||
else
|
||||
cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(ptr));
|
||||
|
||||
if (sts & RCANFD_RFFDSTS_RFESI) {
|
||||
cf->flags |= CANFD_ESI;
|
||||
netdev_dbg(priv->ndev, "ESI Error\n");
|
||||
}
|
||||
|
||||
if (id & RCANFD_RFID_RFIDE)
|
||||
cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
|
||||
else
|
||||
cf->can_id = id & CAN_SFF_MASK;
|
||||
|
||||
if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
|
||||
cf->can_id |= CAN_RTR_FLAG;
|
||||
} else {
|
||||
if (sts & RCANFD_RFFDSTS_RFBRS)
|
||||
cf->flags |= CANFD_BRS;
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
if (sts & RCANFD_RFFDSTS_RFFDF)
|
||||
cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
|
||||
else
|
||||
cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
|
||||
|
||||
rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
|
||||
if (sts & RCANFD_RFFDSTS_RFESI) {
|
||||
cf->flags |= CANFD_ESI;
|
||||
netdev_dbg(priv->ndev, "ESI Error\n");
|
||||
}
|
||||
|
||||
if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
|
||||
cf->can_id |= CAN_RTR_FLAG;
|
||||
} else {
|
||||
if (sts & RCANFD_RFFDSTS_RFBRS)
|
||||
cf->flags |= CANFD_BRS;
|
||||
|
||||
rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
|
||||
}
|
||||
} else {
|
||||
cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
|
||||
if (id & RCANFD_RFID_RFRTR)
|
||||
cf->can_id |= CAN_RTR_FLAG;
|
||||
else
|
||||
rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
|
||||
}
|
||||
|
||||
/* Write 0xff to RFPC to increment the CPU-side
|
||||
@ -1428,13 +1544,19 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
|
||||
priv->can.clock.freq = fcan_freq;
|
||||
dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
|
||||
|
||||
priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
|
||||
priv->can.data_bittiming_const =
|
||||
&rcar_canfd_data_bittiming_const;
|
||||
if (gpriv->fdmode) {
|
||||
priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
|
||||
priv->can.data_bittiming_const =
|
||||
&rcar_canfd_data_bittiming_const;
|
||||
|
||||
/* Controller starts in CAN FD only mode */
|
||||
can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
|
||||
priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
|
||||
/* Controller starts in CAN FD only mode */
|
||||
can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
|
||||
priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
|
||||
} else {
|
||||
/* Controller starts in Classical CAN only mode */
|
||||
priv->can.bittiming_const = &rcar_canfd_bittiming_const;
|
||||
priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
|
||||
}
|
||||
|
||||
priv->can.do_set_mode = rcar_canfd_do_set_mode;
|
||||
priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
|
||||
@ -1482,6 +1604,10 @@ static int rcar_canfd_probe(struct platform_device *pdev)
|
||||
struct device_node *of_child;
|
||||
unsigned long channels_mask = 0;
|
||||
int err, ch_irq, g_irq;
|
||||
bool fdmode = true; /* CAN FD only mode - default */
|
||||
|
||||
if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
|
||||
fdmode = false; /* Classical CAN only mode */
|
||||
|
||||
of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
|
||||
if (of_child && of_device_is_available(of_child))
|
||||
@ -1513,6 +1639,7 @@ static int rcar_canfd_probe(struct platform_device *pdev)
|
||||
}
|
||||
gpriv->pdev = pdev;
|
||||
gpriv->channels_mask = channels_mask;
|
||||
gpriv->fdmode = fdmode;
|
||||
|
||||
/* Peripheral clock */
|
||||
gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
|
||||
@ -1623,8 +1750,8 @@ static int rcar_canfd_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, gpriv);
|
||||
dev_info(&pdev->dev, "global operational state (clk %d)\n",
|
||||
gpriv->fcan);
|
||||
dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
|
||||
gpriv->fcan, gpriv->fdmode);
|
||||
return 0;
|
||||
|
||||
fail_channel:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user