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mtd: rawnand: denali_dt: add more clocks based on IP datasheet
Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run This commit supports these named clocks to represent the real hardware. For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Richard Weinberger <richard@nod.at> Tested-by: Richard Weinberger <richard@nod.at> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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@ -27,7 +27,9 @@
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struct denali_dt {
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struct denali_nand_info denali;
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struct clk *clk;
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struct clk *clk; /* core clock */
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struct clk *clk_x; /* bus interface clock */
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struct clk *clk_ecc; /* ECC circuit clock */
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};
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struct denali_dt_data {
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@ -115,28 +117,61 @@ static int denali_dt_probe(struct platform_device *pdev)
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if (IS_ERR(denali->host))
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return PTR_ERR(denali->host);
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dt->clk = devm_clk_get(dev, NULL);
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/*
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* A single anonymous clock is supported for the backward compatibility.
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* New platforms should support all the named clocks.
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*/
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dt->clk = devm_clk_get(dev, "nand");
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if (IS_ERR(dt->clk))
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dt->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(dt->clk)) {
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dev_err(dev, "no clk available\n");
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return PTR_ERR(dt->clk);
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}
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dt->clk_x = devm_clk_get(dev, "nand_x");
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if (IS_ERR(dt->clk_x))
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dt->clk_x = NULL;
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dt->clk_ecc = devm_clk_get(dev, "ecc");
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if (IS_ERR(dt->clk_ecc))
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dt->clk_ecc = NULL;
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ret = clk_prepare_enable(dt->clk);
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if (ret)
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return ret;
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/*
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* Hardcode the clock rate for the backward compatibility.
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* This works for both SOCFPGA and UniPhier.
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*/
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denali->clk_x_rate = 200000000;
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ret = clk_prepare_enable(dt->clk_x);
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if (ret)
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goto out_disable_clk;
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ret = clk_prepare_enable(dt->clk_ecc);
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if (ret)
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goto out_disable_clk_x;
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if (dt->clk_x) {
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denali->clk_x_rate = clk_get_rate(dt->clk_x);
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} else {
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/*
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* Hardcode the clock rates for the backward compatibility.
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* This works for both SOCFPGA and UniPhier.
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*/
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dev_notice(dev,
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"necessary clock is missing. default clock rates are used.\n");
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denali->clk_x_rate = 200000000;
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}
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ret = denali_init(denali);
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if (ret)
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goto out_disable_clk;
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goto out_disable_clk_ecc;
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platform_set_drvdata(pdev, dt);
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return 0;
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out_disable_clk_ecc:
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clk_disable_unprepare(dt->clk_ecc);
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out_disable_clk_x:
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clk_disable_unprepare(dt->clk_x);
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out_disable_clk:
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clk_disable_unprepare(dt->clk);
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@ -148,6 +183,8 @@ static int denali_dt_remove(struct platform_device *pdev)
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struct denali_dt *dt = platform_get_drvdata(pdev);
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denali_remove(&dt->denali);
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clk_disable_unprepare(dt->clk_ecc);
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clk_disable_unprepare(dt->clk_x);
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clk_disable_unprepare(dt->clk);
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return 0;
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