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drm/i915: Add Pipe D cursor ctrl register for Gen12
Currently the offset for PIPE D cursor control register is missing in i915_reg.h due to which the cursor plane cannot be enabled for Pipe D. This also causes kernel Warning, when a user requests to enable cursor plane for PIPE D for Gen 12 platforms. This patch adds the CURSOR_CTL_D register in the i915_reg.h. v2: Rebase Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111640 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> [Lucas: remove extra blank line] Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1569310312-12313-1-git-send-email-ankit.k.nautiyal@intel.com
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@ -118,6 +118,14 @@
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[PIPE_C] = IVB_CURSOR_C_OFFSET, \
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[PIPE_C] = IVB_CURSOR_C_OFFSET, \
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}
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}
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#define TGL_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = IVB_CURSOR_B_OFFSET, \
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[PIPE_C] = IVB_CURSOR_C_OFFSET, \
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[PIPE_D] = TGL_CURSOR_D_OFFSET, \
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}
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#define I9XX_COLORS \
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#define I9XX_COLORS \
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.color = { .gamma_lut_size = 256 }
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.color = { .gamma_lut_size = 256 }
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#define I965_COLORS \
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#define I965_COLORS \
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@ -787,6 +795,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
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[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
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[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
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[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
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[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
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}, \
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}, \
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TGL_CURSOR_OFFSETS, \
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.has_global_mocs = 1, \
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.has_global_mocs = 1, \
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.display.has_dsb = 1
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.display.has_dsb = 1
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@ -6240,6 +6240,7 @@ enum {
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#define CHV_CURSOR_C_OFFSET 0x700e0
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#define CHV_CURSOR_C_OFFSET 0x700e0
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#define IVB_CURSOR_B_OFFSET 0x71080
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#define IVB_CURSOR_B_OFFSET 0x71080
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#define IVB_CURSOR_C_OFFSET 0x72080
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#define IVB_CURSOR_C_OFFSET 0x72080
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#define TGL_CURSOR_D_OFFSET 0x73080
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/* Display A control */
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/* Display A control */
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#define _DSPACNTR 0x70180
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#define _DSPACNTR 0x70180
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