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ARM: ux500: register all SSP and SPI blocks

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This adds the SSP and SPI blocks to the device tree and makes
them active. Only this way can their clocks be properly gated
off at boot.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2013-10-18 10:25:52 +02:00
parent 72b3e249ce
commit 6e1484c276
1 changed files with 74 additions and 1 deletions
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75
arch/arm/boot/dts/ste-dbx5x0.dtsi
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@ -704,7 +704,80 @@ ssp@80002000 {
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
clock-names = "ssp0clk", "apb_pclk";
dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
<&dma 8 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
};
ssp@80003000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80003000 0x1000>;
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
clock-names = "ssp1clk", "apb_pclk";
dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
<&dma 9 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
};
spi@8011a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8011a000 0x1000>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
clock-names = "spi0clk", "apb_pclk";
dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
<&dma 0 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
};
spi@80112000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80112000 0x1000>;
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
clock-names = "spi1clk", "apb_pclk";
dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
<&dma 35 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
};
spi@80111000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80111000 0x1000>;
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
clock-names = "spi2clk", "apb_pclk";
dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
<&dma 33 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
};
spi@80129000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80129000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
clock-names = "spi3clk", "apb_pclk";
dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
<&dma 40 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
};
uart@80120000 {