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drm/nouveau/mc: s/intr_mask/intr_stat/

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2016-05-30 08:27:22 +10:00
parent 3c2a536b0c
commit 6e09a57899
13 changed files with 19 additions and 19 deletions
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6
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
View File

@ -51,9 +51,9 @@ nvkm_mc_intr_rearm(struct nvkm_device *device)
}
static u32
nvkm_mc_intr_mask(struct nvkm_mc *mc)
nvkm_mc_intr_stat(struct nvkm_mc *mc)
{
u32 intr = mc->func->intr_mask(mc);
u32 intr = mc->func->intr_stat(mc);
if (WARN_ON_ONCE(intr == 0xffffffff))
intr = 0; /* likely fallen off the bus */
return intr;
@ -71,7 +71,7 @@ nvkm_mc_intr(struct nvkm_device *device, bool *handled)
if (unlikely(!mc))
return;
intr = nvkm_mc_intr_mask(mc);
intr = nvkm_mc_intr_stat(mc);
stat = nvkm_top_intr(device, intr, &subdevs);
while (subdevs) {
enum nvkm_devidx subidx = __ffs64(subdevs);

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c
View File

@ -57,7 +57,7 @@ g84_mc = {
.intr = g84_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = g84_mc_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
View File

@ -57,7 +57,7 @@ g98_mc = {
.intr = g98_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = g98_mc_reset,
};

4
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
View File

@ -76,7 +76,7 @@ gf100_mc_intr_rearm(struct nvkm_mc *mc)
}
u32
gf100_mc_intr_mask(struct nvkm_mc *mc)
gf100_mc_intr_stat(struct nvkm_mc *mc)
{
struct nvkm_device *device = mc->subdev.device;
u32 intr0 = nvkm_rd32(device, 0x000100);
@ -96,7 +96,7 @@ gf100_mc = {
.intr = gf100_mc_intr,
.intr_unarm = gf100_mc_intr_unarm,
.intr_rearm = gf100_mc_intr_rearm,
.intr_mask = gf100_mc_intr_mask,
.intr_stat = gf100_mc_intr_stat,
.reset = gf100_mc_reset,
.unk260 = gf100_mc_unk260,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c
View File

@ -52,7 +52,7 @@ gk104_mc = {
.intr = gk104_mc_intr,
.intr_unarm = gf100_mc_intr_unarm,
.intr_rearm = gf100_mc_intr_rearm,
.intr_mask = gf100_mc_intr_mask,
.intr_stat = gf100_mc_intr_stat,
.reset = gk104_mc_reset,
.unk260 = gf100_mc_unk260,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
View File

@ -29,7 +29,7 @@ gk20a_mc = {
.intr = gk104_mc_intr,
.intr_unarm = gf100_mc_intr_unarm,
.intr_rearm = gf100_mc_intr_rearm,
.intr_mask = gf100_mc_intr_mask,
.intr_stat = gf100_mc_intr_stat,
.reset = gk104_mc_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c
View File

@ -59,7 +59,7 @@ gt215_mc = {
.intr = gt215_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = gt215_mc_reset,
};

4
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
View File

@ -56,7 +56,7 @@ nv04_mc_intr_rearm(struct nvkm_mc *mc)
}
u32
nv04_mc_intr_mask(struct nvkm_mc *mc)
nv04_mc_intr_stat(struct nvkm_mc *mc)
{
return nvkm_rd32(mc->subdev.device, 0x000100);
}
@ -75,7 +75,7 @@ nv04_mc = {
.intr = nv04_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = nv04_mc_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c
View File

@ -39,7 +39,7 @@ nv11_mc = {
.intr = nv11_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = nv04_mc_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c
View File

@ -48,7 +48,7 @@ nv17_mc = {
.intr = nv17_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = nv17_mc_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
View File

@ -43,7 +43,7 @@ nv44_mc = {
.intr = nv17_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = nv17_mc_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
View File

@ -50,7 +50,7 @@ nv50_mc = {
.intr = nv50_mc_intr,
.intr_unarm = nv04_mc_intr_unarm,
.intr_rearm = nv04_mc_intr_rearm,
.intr_mask = nv04_mc_intr_mask,
.intr_stat = nv04_mc_intr_stat,
.reset = nv17_mc_reset,
};

6
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
View File

@ -22,7 +22,7 @@ struct nvkm_mc_func {
/* enable reporting of interrupts to host */
void (*intr_rearm)(struct nvkm_mc *);
/* retrieve pending interrupt mask (NV_PMC_INTR) */
u32 (*intr_mask)(struct nvkm_mc *);
u32 (*intr_stat)(struct nvkm_mc *);
const struct nvkm_mc_map *reset;
void (*unk260)(struct nvkm_mc *, u32);
};
@ -30,7 +30,7 @@ struct nvkm_mc_func {
void nv04_mc_init(struct nvkm_mc *);
void nv04_mc_intr_unarm(struct nvkm_mc *);
void nv04_mc_intr_rearm(struct nvkm_mc *);
u32 nv04_mc_intr_mask(struct nvkm_mc *);
u32 nv04_mc_intr_stat(struct nvkm_mc *);
extern const struct nvkm_mc_map nv04_mc_reset[];
extern const struct nvkm_mc_map nv17_mc_intr[];
@ -42,7 +42,7 @@ void nv50_mc_init(struct nvkm_mc *);
void gf100_mc_intr_unarm(struct nvkm_mc *);
void gf100_mc_intr_rearm(struct nvkm_mc *);
u32 gf100_mc_intr_mask(struct nvkm_mc *);
u32 gf100_mc_intr_stat(struct nvkm_mc *);
void gf100_mc_unk260(struct nvkm_mc *, u32);
extern const struct nvkm_mc_map gk104_mc_intr[];