mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-25 00:29:48 +07:00
iwlwifi: remove CSR registers abstraction
We needed this abstraction for some CSR registers for IWL_DEVICE_22560, but that has been removed, so we don't need the abstraction anymore. Remove it. Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
parent
b81b7bd02e
commit
6dece0e99f
@ -77,8 +77,7 @@ static const struct iwl_eeprom_params iwl1000_eeprom_params = {
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.trans.base_params = &iwl1000_base_params, \
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.eeprom_params = &iwl1000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl1000_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 1000 BGN",
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@ -104,8 +103,7 @@ const struct iwl_cfg iwl1000_bg_cfg = {
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.eeprom_params = &iwl1000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.rx_with_siso_diversity = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl100_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 100 BGN",
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@ -103,8 +103,7 @@ static const struct iwl_eeprom_params iwl20x0_eeprom_params = {
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.trans.base_params = &iwl2000_base_params, \
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl2000_2bgn_cfg = {
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@ -131,8 +130,7 @@ const struct iwl_cfg iwl2000_2bgn_d_cfg = {
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.trans.base_params = &iwl2030_base_params, \
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl2030_2bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 2230 BGN",
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@ -153,8 +151,7 @@ const struct iwl_cfg iwl2030_2bgn_cfg = {
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.rx_with_siso_diversity = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl105_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 105 BGN",
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@ -181,8 +178,7 @@ const struct iwl_cfg iwl105_bgn_d_cfg = {
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.rx_with_siso_diversity = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl135_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 135 BGN",
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@ -199,7 +199,6 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
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IWL_DEVICE_22000_COMMON, \
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.trans.device_family = IWL_DEVICE_FAMILY_22000, \
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.trans.base_params = &iwl_22000_base_params, \
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.trans.csr = &iwl_csr_v1, \
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.gp2_reg_addr = 0xa02c68, \
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.mon_dram_regs = { \
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.write_ptr = { \
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@ -217,7 +216,6 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
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.trans.umac_prph_offset = 0x300000, \
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.trans.device_family = IWL_DEVICE_FAMILY_AX210, \
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.trans.base_params = &iwl_ax210_base_params, \
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.trans.csr = &iwl_csr_v1, \
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.min_txq_size = 128, \
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.gp2_reg_addr = 0xd02c68, \
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.min_256_ba_txq_size = 512, \
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@ -75,8 +75,7 @@ static const struct iwl_eeprom_params iwl5000_eeprom_params = {
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.trans.base_params = &iwl5000_base_params, \
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.eeprom_params = &iwl5000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl5300_agn_cfg = {
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.name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
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@ -125,7 +124,6 @@ const struct iwl_cfg iwl5350_agn_cfg = {
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.ht_params = &iwl5000_ht_params,
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.led_mode = IWL_LED_BLINK,
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.internal_wimax_coex = true,
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.trans.csr = &iwl_csr_v1,
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};
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#define IWL_DEVICE_5150 \
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@ -141,8 +139,7 @@ const struct iwl_cfg iwl5350_agn_cfg = {
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.eeprom_params = &iwl5000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.internal_wimax_coex = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl5150_agn_cfg = {
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.name = "Intel(R) WiMAX/WiFi Link 5150 AGN",
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@ -124,8 +124,7 @@ static const struct iwl_eeprom_params iwl6000_eeprom_params = {
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.trans.base_params = &iwl6000_g2_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl6005_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6205 AGN",
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@ -179,8 +178,7 @@ const struct iwl_cfg iwl6005_2agn_mow2_cfg = {
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.trans.base_params = &iwl6000_g2_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl6030_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6230 AGN",
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@ -216,8 +214,7 @@ const struct iwl_cfg iwl6030_2bg_cfg = {
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.trans.base_params = &iwl6000_g2_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl6035_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6235 AGN",
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@ -272,8 +269,7 @@ const struct iwl_cfg iwl130_bg_cfg = {
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.trans.base_params = &iwl6000_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl6000i_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6200 AGN",
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@ -306,8 +302,7 @@ const struct iwl_cfg iwl6000i_2bg_cfg = {
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.internal_wimax_coex = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl6050_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N + WiMAX 6250 AGN",
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@ -333,8 +328,7 @@ const struct iwl_cfg iwl6050_2abg_cfg = {
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.internal_wimax_coex = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.csr = &iwl_csr_v1
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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const struct iwl_cfg iwl6150_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N + WiMAX 6150 BGN",
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@ -361,7 +355,6 @@ const struct iwl_cfg iwl6000_3agn_cfg = {
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.eeprom_params = &iwl6000_eeprom_params,
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.ht_params = &iwl6000_ht_params,
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.led_mode = IWL_LED_BLINK,
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.trans.csr = &iwl_csr_v1,
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};
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MODULE_FIRMWARE(IWL6000_MODULE_FIRMWARE(IWL6000_UCODE_API_MAX));
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@ -154,8 +154,7 @@ static const struct iwl_ht_params iwl7000_ht_params = {
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.nvm_hw_section_num = 0, \
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.non_shared_ant = ANT_A, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.dccm_offset = IWL7000_DCCM_OFFSET, \
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.trans.csr = &iwl_csr_v1
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.dccm_offset = IWL7000_DCCM_OFFSET
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#define IWL_DEVICE_7000 \
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IWL_DEVICE_7000_COMMON, \
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@ -151,8 +151,7 @@ static const struct iwl_tt_params iwl8000_tt_params = {
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.apmg_not_supported = true, \
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.nvm_type = IWL_NVM_EXT, \
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.dbgc_supported = true, \
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.min_umac_error_event_table = 0x800000, \
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.trans.csr = &iwl_csr_v1
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.min_umac_error_event_table = 0x800000
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#define IWL_DEVICE_8000 \
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IWL_DEVICE_8000_COMMON, \
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@ -145,7 +145,6 @@ static const struct iwl_tt_params iwl9000_tt_params = {
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.nvm_type = IWL_NVM_EXT, \
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.dbgc_supported = true, \
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.min_umac_error_event_table = 0x800000, \
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.trans.csr = &iwl_csr_v1, \
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.d3_debug_data_base_addr = 0x401000, \
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.d3_debug_data_length = 92 * 1024, \
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.ht_params = &iwl9000_ht_params, \
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@ -284,52 +284,6 @@ struct iwl_pwr_tx_backoff {
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u32 backoff;
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};
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/**
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* struct iwl_csr_params
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*
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* @flag_sw_reset: reset the device
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* @flag_mac_clock_ready:
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* Indicates MAC (ucode processor, etc.) is powered up and can run.
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* Internal resources are accessible.
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* NOTE: This does not indicate that the processor is actually running.
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* NOTE: This does not indicate that device has completed
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* init or post-power-down restore of internal SRAM memory.
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* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
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* SRAM is restored and uCode is in normal operation mode.
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* This note is relevant only for pre 5xxx devices.
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* NOTE: After device reset, this bit remains "0" until host sets
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* INIT_DONE
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* @flag_init_done: Host sets this to put device into fully operational
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* D0 power mode. Host resets this after SW_RESET to put device into
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* low power mode.
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* @flag_mac_access_req: Host sets this to request and maintain MAC wakeup,
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* to allow host access to device-internal resources. Host must wait for
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* mac_clock_ready (and !GOING_TO_SLEEP) before accessing non-CSR device
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* registers.
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* @flag_val_mac_access_en: mac access is enabled
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* @flag_master_dis: disable master
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* @flag_stop_master: stop master
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* @addr_sw_reset: address for resetting the device
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* @mac_addr0_otp: first part of MAC address from OTP
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* @mac_addr1_otp: second part of MAC address from OTP
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* @mac_addr0_strap: first part of MAC address from strap
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* @mac_addr1_strap: second part of MAC address from strap
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*/
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struct iwl_csr_params {
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u8 flag_sw_reset;
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u8 flag_mac_clock_ready;
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u8 flag_init_done;
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u8 flag_mac_access_req;
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u8 flag_val_mac_access_en;
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u8 flag_master_dis;
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u8 flag_stop_master;
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u8 addr_sw_reset;
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u32 mac_addr0_otp;
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u32 mac_addr1_otp;
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u32 mac_addr0_strap;
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u32 mac_addr1_strap;
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};
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/**
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* struct iwl_cfg_trans - information needed to start the trans
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*
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@ -348,7 +302,6 @@ struct iwl_csr_params {
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*/
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struct iwl_cfg_trans_params {
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const struct iwl_base_params *base_params;
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const struct iwl_csr_params *csr;
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enum iwl_device_family device_family;
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u32 umac_prph_offset;
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u32 rf_id:1,
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@ -499,9 +452,6 @@ struct iwl_cfg {
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const struct iwl_fw_mon_regs mon_smem_regs;
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};
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extern const struct iwl_csr_params iwl_csr_v1;
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extern const struct iwl_csr_params iwl_csr_v2;
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/*
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* This list declares the config structures for all devices.
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*/
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@ -256,6 +256,7 @@
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/* RESET */
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#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
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#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
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#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
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#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
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#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
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#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
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@ -278,11 +279,35 @@
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* 4: GOING_TO_SLEEP
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* Indicates MAC is entering a power-saving sleep power-down.
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* Not a good time to access device-internal resources.
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* 3: MAC_ACCESS_REQ
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* Host sets this to request and maintain MAC wakeup, to allow host
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* access to device-internal resources. Host must wait for
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* MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
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* device registers.
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* 2: INIT_DONE
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* Host sets this to put device into fully operational D0 power mode.
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* Host resets this after SW_RESET to put device into low power mode.
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* 0: MAC_CLOCK_READY
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* Indicates MAC (ucode processor, etc.) is powered up and can run.
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* Internal resources are accessible.
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* NOTE: This does not indicate that the processor is actually running.
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* NOTE: This does not indicate that device has completed
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* init or post-power-down restore of internal SRAM memory.
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* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
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* SRAM is restored and uCode is in normal operation mode.
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* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
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* do not need to save/restore it.
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* NOTE: After device reset, this bit remains "0" until host sets
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* INIT_DONE
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*/
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#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
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#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
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#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
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#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
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#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
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#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
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#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
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#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
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#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
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#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
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@ -70,36 +70,6 @@
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#include "iwl-prph.h"
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#include "iwl-fh.h"
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const struct iwl_csr_params iwl_csr_v1 = {
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.flag_mac_clock_ready = 0,
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.flag_val_mac_access_en = 0,
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.flag_init_done = 2,
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.flag_mac_access_req = 3,
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.flag_sw_reset = 7,
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.flag_master_dis = 8,
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.flag_stop_master = 9,
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.addr_sw_reset = CSR_BASE + 0x020,
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.mac_addr0_otp = 0x380,
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.mac_addr1_otp = 0x384,
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.mac_addr0_strap = 0x388,
|
||||
.mac_addr1_strap = 0x38C
|
||||
};
|
||||
|
||||
const struct iwl_csr_params iwl_csr_v2 = {
|
||||
.flag_init_done = 6,
|
||||
.flag_mac_clock_ready = 20,
|
||||
.flag_val_mac_access_en = 20,
|
||||
.flag_mac_access_req = 21,
|
||||
.flag_master_dis = 28,
|
||||
.flag_stop_master = 29,
|
||||
.flag_sw_reset = 31,
|
||||
.addr_sw_reset = CSR_BASE + 0x024,
|
||||
.mac_addr0_otp = 0x30,
|
||||
.mac_addr1_otp = 0x34,
|
||||
.mac_addr0_strap = 0x38,
|
||||
.mac_addr1_strap = 0x3C
|
||||
};
|
||||
|
||||
void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
|
||||
{
|
||||
trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
|
||||
@ -506,8 +476,7 @@ int iwl_finish_nic_init(struct iwl_trans *trans,
|
||||
* Set "initialization complete" bit to move adapter from
|
||||
* D0U* --> D0A* (powered-up active) state.
|
||||
*/
|
||||
iwl_set_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(cfg_trans->csr->flag_init_done));
|
||||
iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
||||
|
||||
if (cfg_trans->device_family == IWL_DEVICE_FAMILY_8000)
|
||||
udelay(2);
|
||||
@ -518,8 +487,8 @@ int iwl_finish_nic_init(struct iwl_trans *trans,
|
||||
* and accesses to uCode SRAM.
|
||||
*/
|
||||
err = iwl_poll_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(cfg_trans->csr->flag_mac_clock_ready),
|
||||
BIT(cfg_trans->csr->flag_mac_clock_ready),
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
|
||||
25000);
|
||||
if (err < 0)
|
||||
IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
|
||||
|
@ -801,12 +801,8 @@ static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
|
||||
static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
|
||||
struct iwl_nvm_data *data)
|
||||
{
|
||||
__le32 mac_addr0 =
|
||||
cpu_to_le32(iwl_read32(trans,
|
||||
trans->trans_cfg->csr->mac_addr0_strap));
|
||||
__le32 mac_addr1 =
|
||||
cpu_to_le32(iwl_read32(trans,
|
||||
trans->trans_cfg->csr->mac_addr1_strap));
|
||||
__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
|
||||
__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
|
||||
|
||||
iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
|
||||
/*
|
||||
@ -816,10 +812,8 @@ static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
|
||||
if (is_valid_ether_addr(data->hw_addr))
|
||||
return;
|
||||
|
||||
mac_addr0 = cpu_to_le32(iwl_read32(trans,
|
||||
trans->trans_cfg->csr->mac_addr0_otp));
|
||||
mac_addr1 = cpu_to_le32(iwl_read32(trans,
|
||||
trans->trans_cfg->csr->mac_addr1_otp));
|
||||
mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
|
||||
mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
|
||||
|
||||
iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
|
||||
}
|
||||
|
@ -1007,12 +1007,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
/* the trans_cfg should never change, so set it now */
|
||||
iwl_trans->trans_cfg = &cfg->trans;
|
||||
|
||||
if (WARN_ONCE(!iwl_trans->trans_cfg->csr,
|
||||
"CSR addresses aren't configured\n")) {
|
||||
ret = -EINVAL;
|
||||
goto out_free_trans;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_IWLMVM)
|
||||
/*
|
||||
* special-case 7265D, it has the same PCI IDs.
|
||||
|
@ -240,7 +240,7 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
|
||||
IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
|
||||
reg);
|
||||
iwl_set_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
rxq->need_update = true;
|
||||
return;
|
||||
}
|
||||
|
@ -157,8 +157,7 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
|
||||
* Clear "initialization complete" bit to move adapter from
|
||||
* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
|
||||
*/
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_init_done));
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
||||
}
|
||||
|
||||
void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
|
||||
@ -200,7 +199,7 @@ void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
|
||||
|
||||
/* Make sure (redundant) we've released our request to stay awake */
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
|
||||
/* Stop the device, and put it in low power state */
|
||||
iwl_pcie_gen2_apm_stop(trans, false);
|
||||
|
@ -183,8 +183,7 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
|
||||
static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
|
||||
{
|
||||
/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
|
||||
iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
|
||||
BIT(trans->trans_cfg->csr->flag_sw_reset));
|
||||
iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
|
||||
usleep_range(5000, 6000);
|
||||
}
|
||||
|
||||
@ -487,8 +486,7 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
|
||||
* Clear "initialization complete" bit to move adapter from
|
||||
* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
|
||||
*/
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_init_done));
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
||||
|
||||
/* Activates XTAL resources monitor */
|
||||
__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
|
||||
@ -510,12 +508,11 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
|
||||
int ret;
|
||||
|
||||
/* stop device's busmaster DMA activity */
|
||||
iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
|
||||
BIT(trans->trans_cfg->csr->flag_stop_master));
|
||||
iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
|
||||
|
||||
ret = iwl_poll_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
|
||||
BIT(trans->trans_cfg->csr->flag_master_dis),
|
||||
BIT(trans->trans_cfg->csr->flag_master_dis), 100);
|
||||
ret = iwl_poll_bit(trans, CSR_RESET,
|
||||
CSR_RESET_REG_FLAG_MASTER_DISABLED,
|
||||
CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
|
||||
if (ret < 0)
|
||||
IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
|
||||
|
||||
@ -564,8 +561,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
|
||||
* Clear "initialization complete" bit to move adapter from
|
||||
* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
|
||||
*/
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_init_done));
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
||||
}
|
||||
|
||||
static int iwl_pcie_nic_init(struct iwl_trans *trans)
|
||||
@ -1270,7 +1266,7 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
|
||||
|
||||
/* Make sure (redundant) we've released our request to stay awake */
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
|
||||
/* Stop the device, and put it in low power state */
|
||||
iwl_pcie_apm_stop(trans, false);
|
||||
@ -1494,9 +1490,8 @@ void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
|
||||
iwl_pcie_synchronize_irqs(trans);
|
||||
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_init_done));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
||||
|
||||
if (reset) {
|
||||
/*
|
||||
@ -1561,7 +1556,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
|
||||
}
|
||||
|
||||
iwl_set_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
|
||||
ret = iwl_finish_nic_init(trans, trans->trans_cfg);
|
||||
if (ret)
|
||||
@ -1583,7 +1578,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
|
||||
|
||||
if (!reset) {
|
||||
iwl_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
} else {
|
||||
iwl_trans_pcie_tx_reset(trans);
|
||||
|
||||
@ -2029,7 +2024,7 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
|
||||
|
||||
/* this bit wakes up the NIC */
|
||||
__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
|
||||
udelay(2);
|
||||
|
||||
@ -2054,8 +2049,8 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
|
||||
* and do not save/restore SRAM when power cycling.
|
||||
*/
|
||||
ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
|
||||
(BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
|
||||
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
|
||||
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
|
||||
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
|
||||
if (unlikely(ret < 0)) {
|
||||
u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
|
||||
@ -2137,7 +2132,7 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
|
||||
goto out;
|
||||
|
||||
__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
/*
|
||||
* Above we read the CSR_GP_CNTRL register, which will flush
|
||||
* any previous writes, but we need the write that clears the
|
||||
|
@ -306,7 +306,7 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
|
||||
IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
|
||||
txq_id, reg);
|
||||
iwl_set_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
txq->need_update = true;
|
||||
return;
|
||||
}
|
||||
@ -646,7 +646,7 @@ static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
|
||||
|
||||
trans_pcie->cmd_hold_nic_awake = false;
|
||||
__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1255,16 +1255,16 @@ static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
|
||||
if (trans->trans_cfg->base_params->apmg_wake_up_wa &&
|
||||
!trans_pcie->cmd_hold_nic_awake) {
|
||||
__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
|
||||
ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
|
||||
(BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
|
||||
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
|
||||
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
|
||||
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
|
||||
15000);
|
||||
if (ret < 0) {
|
||||
__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
|
||||
BIT(trans->trans_cfg->csr->flag_mac_access_req));
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
||||
IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user