From 2c221f5d41662e1b4a26d09fb953bbe4f4b025b3 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Tue, 28 Feb 2017 16:00:26 +0900 Subject: [PATCH 01/10] ARM: dts: exynos: Add phy-pcie node for pcie to Exynos5440 Add pcie-phy node to phy-exynos-pcie along with some changes to other nodes: 1. Remove the configuration space from "ranges" property because this was the old way of getting it. Preferred is to use "config" reg. 2. Use the reg-names as "elbi" and "config" so the purpose of addresses will be easily known. Signed-off-by: Jaehoon Chung Reviewed-by: Pankaj Dubey Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5440.dtsi | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 77d35bb92950..f3ac53af9cdb 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -290,11 +290,22 @@ ehci@221000 { clock-names = "usbhost"; }; + pcie_phy0: pcie-phy@270000 { + #phy-cells = <0>; + compatible = "samsung,exynos5440-pcie-phy"; + reg = <0x270000 0x1000>, <0x271000 0x40>; + }; + + pcie_phy1: pcie-phy@272000 { + #phy-cells = <0>; + compatible = "samsung,exynos5440-pcie-phy"; + reg = <0x272000 0x1000>, <0x271040 0x40>; + }; + pcie_0: pcie@290000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000 - 0x270000 0x1000 - 0x271000 0x40>; + reg = <0x290000 0x1000>, <0x40000000 0x1000>; + reg-names = "elbi", "config"; interrupts = , , ; @@ -303,8 +314,8 @@ pcie_0: pcie@290000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + phys = <&pcie_phy0>; + ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; @@ -315,9 +326,8 @@ pcie_0: pcie@290000 { pcie_1: pcie@2a0000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000 - 0x272000 0x1000 - 0x271040 0x40>; + reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; + reg-names = "elbi", "config"; interrupts = , , ; @@ -326,8 +336,8 @@ pcie_1: pcie@2a0000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + phys = <&pcie_phy1>; + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; From 28928a3ce142b2e4e5a7a0f067cefb41a3d2c3f9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Feb 2017 22:14:56 +0200 Subject: [PATCH 02/10] ARM: dts: exynos: Do not ignore real-world fuse values for thermal zone 0 on Exynos5420 In Odroid XU3 Lite board, the temperature levels reported for thermal zone 0 were weird. In warm room: /sys/class/thermal/thermal_zone0/temp:32000 /sys/class/thermal/thermal_zone1/temp:51000 /sys/class/thermal/thermal_zone2/temp:55000 /sys/class/thermal/thermal_zone3/temp:54000 /sys/class/thermal/thermal_zone4/temp:51000 Sometimes after booting the value was even equal to ambient temperature which is highly unlikely to be a real temperature of sensor in SoC. The thermal sensor's calibration (trimming) is based on fused values. In case of the board above, the fused values are: 35, 52, 43, 58 and 43 (corresponding to each TMU device). However driver defined a minimum value for fused data as 40 and for smaller values it was using a hard-coded 55 instead. This lead to mapping data from sensor to wrong temperatures for thermal zone 0. Various vendor 3.10 trees (Hardkernel's based on Samsung LSI, Artik 10) do not impose any limits on fused values. Since we do not have any knowledge about these limits, use 0 as a minimum accepted fused value. This should essentially allow accepting any reasonable fused value thus behaving like vendor driver. The exynos5420-tmu-sensor-conf.dtsi is copied directly from existing exynos4412 with one change - the samsung,tmu_min_efuse_value. Signed-off-by: Krzysztof Kozlowski Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Eduardo Valentin Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Reviewed-by: Anand Moon Tested-by: Anand Moon --- .../boot/dts/exynos5420-tmu-sensor-conf.dtsi | 25 +++++++++++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 10 ++++---- 2 files changed, 30 insertions(+), 5 deletions(-) create mode 100644 arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi diff --git a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi new file mode 100644 index 000000000000..c8771c660550 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi @@ -0,0 +1,25 @@ +/* + * Device tree sources for Exynos5420 TMU sensor configuration + * + * Copyright (c) 2014 Lukasz Majewski + * Copyright (c) 2017 Krzysztof Kozlowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +#thermal-sensor-cells = <0>; +samsung,tmu_gain = <8>; +samsung,tmu_reference_voltage = <16>; +samsung,tmu_noise_cancel_mode = <4>; +samsung,tmu_efuse_value = <55>; +samsung,tmu_min_efuse_value = <0>; +samsung,tmu_max_efuse_value = <100>; +samsung,tmu_first_point_trim = <25>; +samsung,tmu_second_point_trim = <85>; +samsung,tmu_default_temp_offset = <50>; +samsung,tmu_cal_type = ; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 7dc9dc82afd8..83b3899d228d 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -699,7 +699,7 @@ tmu_cpu0: tmu@10060000 { interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #include "exynos5420-tmu-sensor-conf.dtsi" }; tmu_cpu1: tmu@10064000 { @@ -708,7 +708,7 @@ tmu_cpu1: tmu@10064000 { interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #include "exynos5420-tmu-sensor-conf.dtsi" }; tmu_cpu2: tmu@10068000 { @@ -717,7 +717,7 @@ tmu_cpu2: tmu@10068000 { interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #include "exynos5420-tmu-sensor-conf.dtsi" }; tmu_cpu3: tmu@1006c000 { @@ -726,7 +726,7 @@ tmu_cpu3: tmu@1006c000 { interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #include "exynos5420-tmu-sensor-conf.dtsi" }; tmu_gpu: tmu@100a0000 { @@ -735,7 +735,7 @@ tmu_gpu: tmu@100a0000 { interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #include "exynos5420-tmu-sensor-conf.dtsi" }; sysmmu_g2dr: sysmmu@0x10A60000 { From 4c74ea4e20b582bf90a2cf509d88aa7c2dbffb12 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 8 Mar 2017 13:54:09 +0900 Subject: [PATCH 03/10] ARM: dts: exynos: Add the burst and esc clock frequency properties to DSI node Add the burst and esc clock frequency properties to the parent (DSI node). Currently the clock is parsed from the port node, while it should be taken from the dsi node. Signed-off-by: Hoegeun Kwon Reviewed-by: Andrzej Hajda Reviewed-by: Andi Shyti Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-rinato.dts | 2 ++ arch/arm/boot/dts/exynos4210-trats.dts | 2 ++ arch/arm/boot/dts/exynos4412-trats2.dts | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 548413e23c47..c9f191ca7b9c 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -215,6 +215,8 @@ &hsotg { &dsi_0 { vddcore-supply = <&ldo6_reg>; vddio-supply = <&ldo6_reg>; + samsung,burst-clock-frequency = <250000000>; + samsung,esc-clock-frequency = <20000000>; samsung,pll-clock-frequency = <24000000>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 0ca1b4d355f2..1743ca850070 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -197,6 +197,8 @@ &cpu0 { &dsi_0 { vddcore-supply = <&vusb_reg>; vddio-supply = <&vmipi_reg>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; samsung,pll-clock-frequency = <24000000>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 41ecd6d465a7..82221a00444d 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -385,6 +385,8 @@ csis1_ep: endpoint { &dsi_0 { vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; samsung,pll-clock-frequency = <24000000>; status = "okay"; From bdc42353ba3dd3619b6186748701f87ecc8e7458 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2017 19:25:22 +0200 Subject: [PATCH 04/10] ARM: dts: exynos: Fix watchdog reset on Exynos4412 The Exynos4412 has the same watchdog as newer SoCs (e.g. Exynos5250). Just like the others, for working it requires additional steps in Power Management Unit: unmasking the reset request and enabling the system reset. Without these additional steps in PMU, the watchdog will not be able to reset the system on expiration event. Change the compatible of Exynos4412 watchdog device node to samsung,exynos5250-wdt which includes the additional PMU steps. This will also fix infinite watchdog interrupt in soft mode (lack of interrupt clear) because it is also included in samsung,exynos5250-wdt. Signed-off-by: Krzysztof Kozlowski Acked-by: Guenter Roeck --- arch/arm/boot/dts/exynos4.dtsi | 9 --------- arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4412.dtsi | 10 ++++++++++ 3 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 18def1c774d5..71e2cdae6068 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -283,15 +283,6 @@ csis_1: csis@11890000 { }; }; - watchdog: watchdog@10060000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - status = "disabled"; - }; - rtc: rtc@10070000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index f9408188f97f..8bff2253acca 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -119,6 +119,15 @@ mct_map: mct-map { }; }; + watchdog: watchdog@10060000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + status = "disabled"; + }; + clock: clock-controller@10030000 { compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 235bbb69ad7c..6f47988a1ab5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -215,6 +215,16 @@ mct_map: mct-map { }; }; + watchdog: watchdog@10060000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + adc: adc@126C0000 { compatible = "samsung,exynos-adc-v1"; reg = <0x126C0000 0x100>; From b5acdc38b8ceba1b642ba354be8845a8ac2b35d1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2017 19:25:23 +0200 Subject: [PATCH 05/10] ARM: dts: s3c64xx: Enable watchdog on all S3C64xx boards Watchdog module does not have external dependencies so it can be safely enabled in s3c64xx.dtsi thus making it available for all S3C64xx-based boards. Signed-off-by: Krzysztof Kozlowski Acked-by: Guenter Roeck --- arch/arm/boot/dts/s3c64xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index 0ccb414cd268..6caec5f27d38 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -100,7 +100,6 @@ watchdog: watchdog@7e004000 { interrupts = <26>; clock-names = "watchdog"; clocks = <&clocks PCLK_WDT>; - status = "disabled"; }; i2c0: i2c@7f004000 { From de44097b256146fb633f843b250f2515b838e031 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2017 19:25:24 +0200 Subject: [PATCH 06/10] ARM: dts: exynos: Enable watchdog on all Exynos4 boards Watchdog module does not have external dependencies so it can be safely enabled in exynos4.dtsi thus making it available for all Exynos4-based boards. Signed-off-by: Krzysztof Kozlowski Acked-by: Guenter Roeck --- arch/arm/boot/dts/exynos4210-origen.dts | 4 ---- arch/arm/boot/dts/exynos4210.dtsi | 1 - arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 4 ---- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 ---- arch/arm/boot/dts/exynos4412-origen.dts | 4 ---- arch/arm/boot/dts/exynos4412.dtsi | 1 - 6 files changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index a2c6a13fe67b..312650e2450f 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -328,7 +328,3 @@ &rtc { &tmu { status = "okay"; }; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 8bff2253acca..9d51d4d62d94 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -125,7 +125,6 @@ watchdog: watchdog@10060000 { interrupts = ; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; - status = "disabled"; }; clock: clock-controller@10030000 { diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index a36cd36a26b8..4cd62487bb16 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -495,7 +495,3 @@ &tmu { vtmu-supply = <&ldo16_reg>; status = "okay"; }; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 78f118cb73d4..0f1ff792fe44 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -555,7 +555,3 @@ &tmu { vtmu-supply = <&ldo10_reg>; status = "okay"; }; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index a1ab6f94bb64..7a83e2df18a6 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -541,7 +541,3 @@ &serial_2 { &serial_3 { status = "okay"; }; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 6f47988a1ab5..cc69466f17c0 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -222,7 +222,6 @@ watchdog: watchdog@10060000 { clocks = <&clock CLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; }; adc: adc@126C0000 { From 7e93df3526b5dfc0ea76cb01041d7057f9fae478 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2017 19:25:25 +0200 Subject: [PATCH 07/10] ARM: dts: exynos: Fix infinite interrupt in soft mode on Exynos4210 and Exynos5440 In soft (no-reboot) mode, the driver self-pings watchdog upon expiration of an interrupt. The interrupt has to be cleared, because otherwise system enters infinite interrupt handling loop. Use a samsung,s3c6410-wdt compatible to select appropriate quirk for clearing the watchdog interrupt. Signed-off-by: Krzysztof Kozlowski Acked-by: Guenter Roeck Reviewed-by: Bartlomiej Zolnierkiewicz --- arch/arm/boot/dts/exynos4210.dtsi | 2 +- arch/arm/boot/dts/exynos5440.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 9d51d4d62d94..e6e62103a71f 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -120,7 +120,7 @@ mct_map: mct-map { }; watchdog: watchdog@10060000 { - compatible = "samsung,s3c2410-wdt"; + compatible = "samsung,s3c6410-wdt"; reg = <0x10060000 0x100>; interrupts = ; clocks = <&clock CLK_WDT>; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index f3ac53af9cdb..a4ea018464fc 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -189,7 +189,7 @@ i2c@100000 { }; watchdog@110000 { - compatible = "samsung,s3c2410-wdt"; + compatible = "samsung,s3c6410-wdt"; reg = <0x110000 0x1000>; interrupts = ; clocks = <&clock CLK_B_125>; From 9f55342cc2de36d0720df1e7fc902eac82c145cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2017 19:25:26 +0200 Subject: [PATCH 08/10] ARM: dts: s3c64xx: Fix infinite interrupt in soft mode In soft (no-reboot) mode, the driver self-pings watchdog upon expiration of an interrupt. The interrupt has to be cleared, because otherwise system enters infinite interrupt handling loop. Use a samsung,s3c6410-wdt compatible to select appropriate quirk for clearing the watchdog interrupt. Signed-off-by: Krzysztof Kozlowski Acked-by: Guenter Roeck Reviewed-by: Bartlomiej Zolnierkiewicz --- arch/arm/boot/dts/s3c64xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index 6caec5f27d38..c55cbb3af2c0 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -94,7 +94,7 @@ sdhci2: sdhci@7c400000 { }; watchdog: watchdog@7e004000 { - compatible = "samsung,s3c2410-wdt"; + compatible = "samsung,s3c6410-wdt"; reg = <0x7e004000 0x1000>; interrupt-parent = <&vic0>; interrupts = <26>; From c70d219bef3a2636c8220368a71436c339f9ae2e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2017 19:25:27 +0200 Subject: [PATCH 09/10] ARM: dts: s5pv210: Fix infinite interrupt in soft mode In soft (no-reboot) mode, the driver self-pings watchdog upon expiration of an interrupt. The interrupt has to be cleared, because otherwise system enters infinite interrupt handling loop. Use a samsung,s3c6410-wdt compatible to select appropriate quirk for clearing the watchdog interrupt. Signed-off-by: Krzysztof Kozlowski Acked-by: Guenter Roeck Reviewed-by: Bartlomiej Zolnierkiewicz --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index a853918be43f..726c5d0dbd5b 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -310,7 +310,7 @@ pwm: pwm@e2500000 { }; watchdog: watchdog@e2700000 { - compatible = "samsung,s3c2410-wdt"; + compatible = "samsung,s3c6410-wdt"; reg = <0xe2700000 0x1000>; interrupt-parent = <&vic0>; interrupts = <26>; From 192c1df4a75499a6ab70aca38c6a7e5e40013d77 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Wed, 29 Mar 2017 16:15:37 +0200 Subject: [PATCH 10/10] ARM: dts: exynos: add HDMI controller phandle to exynos4.dtsi Add the new hdmi phandle to exynos4.dtsi. This phandle is needed by the s5p-cec driver to initialize the CEC notifier framework. Tested with my Odroid U3. Signed-off-by: Hans Verkuil Tested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 18def1c774d5..84fcdff140ae 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -771,6 +771,7 @@ hdmicec: cec@100B0000 { clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; status = "disabled";