From ee4ee527278a66321301d4f1f5ae22e49ab18fad Mon Sep 17 00:00:00 2001 From: Chris Torek Date: Wed, 3 Dec 2008 00:47:28 -0800 Subject: [PATCH 1/4] sparc64: Fix bug in PTRACE_SETFPREGS64 handling. From: Chris Torek >The SPARC64 kernel code for PTRACE_SETFPREGS64 appears to be an exact copy >of that for PTRACE_GETFPREGS64. This means that gdbserver and native >64-bit GDB cannot set floating-point registers. It looks like a simple typo. Signed-off-by: David S. Miller --- arch/sparc64/kernel/ptrace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c index f43adbc773ca..a941c610e7ce 100644 --- a/arch/sparc64/kernel/ptrace.c +++ b/arch/sparc64/kernel/ptrace.c @@ -1014,7 +1014,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) break; case PTRACE_SETFPREGS64: - ret = copy_regset_to_user(child, view, REGSET_FP, + ret = copy_regset_from_user(child, view, REGSET_FP, 0 * sizeof(u64), 33 * sizeof(u64), fps); From e8e8e80ee047b131a0cd6a3e96e0f8dfa14f6d99 Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Wed, 3 Dec 2008 16:04:52 -0800 Subject: [PATCH 2/4] sparc: asm/bitops.h should define __fls bitops_64.h includes the generic one; pretty sure 32 should too. (Found by using __fls in generic code and breaking sparc defconfig build: thanks Stephen and linux-next!) Signed-off-by: Rusty Russell Signed-off-by: David S. Miller --- arch/sparc/include/asm/bitops_32.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h index 68b98a7e6454..9cf4ae0cd7ba 100644 --- a/arch/sparc/include/asm/bitops_32.h +++ b/arch/sparc/include/asm/bitops_32.h @@ -98,6 +98,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) #include #include #include +#include #include #include #include From 726c12f57d7e3ff43693d88e13b1ff02464c75d3 Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Wed, 3 Dec 2008 19:36:05 -0800 Subject: [PATCH 3/4] sparc64: Fix VIS emulation bugs This patch fixes some bugs in VIS emulation that cause the GCC test failure FAIL: gcc.target/sparc/pdist-3.c execution test for both 32-bit and 64-bit testing on hardware lacking these instructions. The emulation code for the pdist instruction uses RS1(insn) for both source registers rs1 and rs2, which is obviously wrong and leads to the instruction doing nothing (the observed problem), and further inspection of the code shows that RS1 uses a shift of 24 and RD a shift of 25, which clearly cannot both be right; examining SPARC documentation indicates the correct shift for RS1 is 14. This patch fixes the bug if single-stepping over the affected instruction in the debugger, but not if the testcase is run standalone. For that, Wind River has another patch I hope they will send as a followup to this patch submission. Signed-off-by: Joseph Myers Signed-off-by: David S. Miller --- arch/sparc64/kernel/visemul.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sparc64/kernel/visemul.c b/arch/sparc64/kernel/visemul.c index 9e05cb5cb855..69f8a35c6bcd 100644 --- a/arch/sparc64/kernel/visemul.c +++ b/arch/sparc64/kernel/visemul.c @@ -131,7 +131,7 @@ #define VIS_OPF_SHIFT 5 #define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT) -#define RS1(INSN) (((INSN) >> 24) & 0x1f) +#define RS1(INSN) (((INSN) >> 14) & 0x1f) #define RS2(INSN) (((INSN) >> 0) & 0x1f) #define RD(INSN) (((INSN) >> 25) & 0x1f) @@ -445,7 +445,7 @@ static void pdist(struct pt_regs *regs, unsigned int insn) unsigned long i; rs1 = fpd_regval(f, RS1(insn)); - rs2 = fpd_regval(f, RS1(insn)); + rs2 = fpd_regval(f, RS2(insn)); rd = fpd_regaddr(f, RD(insn)); rd_val = *rd; From 410d2c8187ed969238ba98008c1d57307a56cfd8 Mon Sep 17 00:00:00 2001 From: "Hong H. Pham" Date: Thu, 4 Dec 2008 09:12:57 -0800 Subject: [PATCH 4/4] sparc64: Sync FPU state in VIS emulation handler. Copy the FPU state to the task's thread_info->fpregs for the VIS emulation functions to access. Signed-off-by: Hong H. Pham Signed-off-by: David S. Miller --- arch/sparc64/kernel/visemul.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/sparc64/kernel/visemul.c b/arch/sparc64/kernel/visemul.c index 69f8a35c6bcd..b956fd71c131 100644 --- a/arch/sparc64/kernel/visemul.c +++ b/arch/sparc64/kernel/visemul.c @@ -807,6 +807,8 @@ int vis_emul(struct pt_regs *regs, unsigned int insn) if (get_user(insn, (u32 __user *) pc)) return -EFAULT; + save_and_clear_fpu(); + opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT; switch (opf) { default: