mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/display: Restructuring and cleaning up DML
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
Alex Deucher
parent
19b7fe4a48
commit
6d04ee9dc1
@ -27,20 +27,36 @@
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float dcn_bw_mod(const float arg1, const float arg2)
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{
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if (arg1 != arg1)
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return arg2;
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if (arg2 != arg2)
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return arg1;
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return arg1 - arg1 * ((int) (arg1 / arg2));
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}
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float dcn_bw_min2(const float arg1, const float arg2)
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{
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if (arg1 != arg1)
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return arg2;
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if (arg2 != arg2)
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return arg1;
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return arg1 < arg2 ? arg1 : arg2;
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}
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unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
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{
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if (arg1 != arg1)
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return arg2;
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if (arg2 != arg2)
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return arg1;
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return arg1 > arg2 ? arg1 : arg2;
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}
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float dcn_bw_max2(const float arg1, const float arg2)
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{
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if (arg1 != arg1)
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return arg2;
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if (arg2 != arg2)
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return arg1;
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return arg1 > arg2 ? arg1 : arg2;
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}
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@ -386,10 +386,6 @@ static void pipe_ctx_to_e2e_pipe_params (
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- pipe->stream->timing.v_addressable
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- pipe->stream->timing.v_border_bottom
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- pipe->stream->timing.v_border_top;
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input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total
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- pipe->stream->timing.v_addressable
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- pipe->stream->timing.v_front_porch;
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input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
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input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
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input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
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@ -459,9 +455,9 @@ static void dcn_bw_calc_rq_dlg_ttu(
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/*todo: soc->sr_enter_plus_exit_time??*/
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dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
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dml_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
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extract_rq_regs(dml, rq_regs, rq_param);
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dml_rq_dlg_get_dlg_params(
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dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
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dml1_extract_rq_regs(dml, rq_regs, rq_param);
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dml1_rq_dlg_get_dlg_params(
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dml,
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dlg_regs,
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ttu_regs,
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@ -474,96 +470,6 @@ static void dcn_bw_calc_rq_dlg_ttu(
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pipe->plane_state->flip_immediate);
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}
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static void dcn_dml_wm_override(
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const struct dcn_bw_internal_vars *v,
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struct display_mode_lib *dml,
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struct dc_state *context,
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const struct resource_pool *pool)
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{
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int i, in_idx, active_count;
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struct _vcs_dpi_display_e2e_pipe_params_st *input = kzalloc(pool->pipe_count * sizeof(struct _vcs_dpi_display_e2e_pipe_params_st),
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GFP_KERNEL);
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struct wm {
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double urgent;
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struct _vcs_dpi_cstate_pstate_watermarks_st cpstate;
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double pte_meta_urgent;
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} a;
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for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
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if (!pipe->stream || !pipe->plane_state)
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continue;
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input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
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input[in_idx].clks_cfg.dispclk_mhz = v->dispclk;
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input[in_idx].clks_cfg.dppclk_mhz = v->dppclk;
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input[in_idx].clks_cfg.refclk_mhz = pool->ref_clock_inKhz / 1000;
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input[in_idx].clks_cfg.socclk_mhz = v->socclk;
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input[in_idx].clks_cfg.voltage = v->voltage_level;
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input[in_idx].dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
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input[in_idx].dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
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//input[in_idx].dout.output_standard;
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switch (v->output_deep_color[in_idx]) {
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case dcn_bw_encoder_12bpc:
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input[in_idx].dout.output_bpc = dm_out_12;
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break;
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case dcn_bw_encoder_10bpc:
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input[in_idx].dout.output_bpc = dm_out_10;
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break;
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case dcn_bw_encoder_8bpc:
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default:
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input[in_idx].dout.output_bpc = dm_out_8;
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break;
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}
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pipe_ctx_to_e2e_pipe_params(pipe, &input[in_idx].pipe);
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dml_rq_dlg_get_rq_reg(
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dml,
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&pipe->rq_regs,
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input[in_idx].pipe.src);
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in_idx++;
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}
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active_count = in_idx;
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a.urgent = dml_wm_urgent_e2e(dml, input, active_count);
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a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);
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a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);
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context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
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a.cpstate.cstate_exit_us * 1000;
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context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
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a.cpstate.cstate_enter_plus_exit_us * 1000;
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context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
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a.cpstate.pstate_change_us * 1000;
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context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
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context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000;
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context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
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context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
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context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
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for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
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if (!pipe->stream || !pipe->plane_state)
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continue;
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dml_rq_dlg_get_dlg_reg(dml,
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&pipe->dlg_regs,
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&pipe->ttu_regs,
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input, active_count,
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in_idx,
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true,
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true,
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v->pte_enable == dcn_bw_yes,
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pipe->plane_state->flip_immediate);
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in_idx++;
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}
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kfree(input);
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}
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static void split_stream_across_pipes(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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@ -1163,9 +1069,6 @@ bool dcn_validate_bandwidth(
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input_idx++;
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}
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if (dc->debug.use_dml_wm)
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dcn_dml_wm_override(v, (struct display_mode_lib *)
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&dc->dml, context, pool);
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}
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if (v->voltage_level == 0) {
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@ -200,7 +200,6 @@ struct dc_debug {
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bool disable_hubp_power_gate;
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bool disable_pplib_wm_range;
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enum wm_report_mode pplib_wm_report_mode;
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bool use_dml_wm;
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unsigned int min_disp_clk_khz;
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int sr_exit_time_dpm0_ns;
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int sr_enter_plus_exit_time_dpm0_ns;
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@ -425,8 +425,6 @@ static const struct dc_debug debug_defaults_drv = {
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.disable_pplib_clock_request = true,
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.disable_pplib_wm_range = false,
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.pplib_wm_report_mode = WM_REPORT_DEFAULT,
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.use_dml_wm = false,
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.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
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.disable_dcc = DCC_ENABLE,
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.voltage_align_fclk = true,
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@ -439,8 +437,7 @@ static const struct dc_debug debug_defaults_diags = {
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.clock_trace = true,
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.disable_stutter = true,
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.disable_pplib_clock_request = true,
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.disable_pplib_wm_range = true,
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.use_dml_wm = false,
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.disable_pplib_wm_range = true
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};
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static void dcn10_dpp_destroy(struct transform **xfm)
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@ -3,19 +3,19 @@
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# It provides the general basic services required by other DAL
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# subcomponents.
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CFLAGS_display_mode_vba.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_watermark.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_mode_support.o := -mhard-float -msse -mpreferred-stack-boundary=4
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DML = display_mode_lib.o display_pipe_clocks.o display_rq_dlg_calc.o \
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display_rq_dlg_helpers.o display_watermark.o \
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soc_bounding_box.o dml_common_defs.o display_mode_support.o
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display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
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soc_bounding_box.o dml_common_defs.o display_mode_vba.o
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AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
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@ -25,9 +25,11 @@
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#ifndef __DC_FEATURES_H__
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#define __DC_FEATURES_H__
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// local features
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#define DC__PRESENT 1
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#define DC__PRESENT__1 1
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#define DC__NUM_DPP 4
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#define DC__VOLTAGE_STATES 7
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#define DC__NUM_DPP__4 1
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#define DC__NUM_DPP__0_PRESENT 1
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#define DC__NUM_DPP__1_PRESENT 1
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@ -24,14 +24,12 @@
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*/
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#ifndef __DISPLAY_MODE_ENUMS_H__
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#define __DISPLAY_MODE_ENUMS_H__
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enum output_encoder_class {
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dm_dp = 0,
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dm_hdmi = 1,
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dm_wb = 2
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dm_dp = 0, dm_hdmi = 1, dm_wb = 2
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};
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enum output_format_class {
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dm_444 = 0,
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dm_420 = 1
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dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
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};
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enum source_format_class {
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dm_444_16 = 0,
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@ -40,18 +38,14 @@ enum source_format_class {
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dm_420_8 = 3,
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dm_420_10 = 4,
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dm_422_8 = 5,
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dm_422_10 = 6
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dm_422_10 = 6,
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dm_444_8 = 7
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};
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enum output_bpc_class {
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dm_out_6 = 0,
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dm_out_8 = 1,
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dm_out_10 = 2,
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dm_out_12 = 3,
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dm_out_16 = 4
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dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
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};
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enum scan_direction_class {
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dm_horz = 0,
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dm_vert = 1
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dm_horz = 0, dm_vert = 1
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};
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enum dm_swizzle_mode {
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dm_sw_linear = 0,
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@ -84,28 +78,30 @@ enum dm_swizzle_mode {
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dm_sw_SPARE_14 = 27,
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dm_sw_SPARE_15 = 28,
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dm_sw_var_s_x = 29,
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dm_sw_var_d_x = 30
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dm_sw_var_d_x = 30,
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dm_sw_64kb_r_x
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};
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enum lb_depth {
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dm_lb_10 = 30,
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dm_lb_8 = 24,
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dm_lb_6 = 18,
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dm_lb_12 = 36
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dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
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};
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enum voltage_state {
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dm_vmin = 0,
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dm_vmid = 1,
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dm_vnom = 2,
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dm_vmax = 3,
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dm_vmax_exceeded = 4
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dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
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};
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enum source_macro_tile_size {
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dm_4k_tile = 0,
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dm_64k_tile = 1,
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dm_256k_tile = 2
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dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
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};
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enum cursor_bpp {
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dm_cur_2bit = 0,
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dm_cur_32bit = 1
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dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
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};
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enum clock_change_support {
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dm_dram_clock_change_uninitialized = 0,
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dm_dram_clock_change_vactive,
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dm_dram_clock_change_vblank,
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dm_dram_clock_change_unsupported
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};
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enum output_standard {
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dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
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};
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#endif
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@ -24,6 +24,7 @@
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*/
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#include "display_mode_lib.h"
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#include "dc_features.h"
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static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
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{
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@ -128,11 +129,7 @@ static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project pro
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static void set_mode_evaluation(struct _vcs_dpi_mode_evaluation_st *me, enum dml_project project)
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{
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if (project == DML_PROJECT_RAVEN1) {
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me->voltage_override = dm_vmin;
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} else {
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BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
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}
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}
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void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
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@ -25,12 +25,13 @@
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#ifndef __DISPLAY_MODE_LIB_H__
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#define __DISPLAY_MODE_LIB_H__
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#include "dml_common_defs.h"
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#include "soc_bounding_box.h"
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#include "display_watermark.h"
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#include "display_mode_vba.h"
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#include "display_pipe_clocks.h"
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#include "display_rq_dlg_calc.h"
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#include "display_mode_support.h"
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#include "dml1_display_rq_dlg_calc.h"
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enum dml_project {
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DML_PROJECT_UNDEFINED,
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@ -42,8 +43,7 @@ struct display_mode_lib {
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struct _vcs_dpi_soc_bounding_box_st soc;
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struct _vcs_dpi_mode_evaluation_st me;
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enum dml_project project;
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struct dml_ms_internal_vars vars;
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struct _vcs_dpi_wm_calc_pipe_params_st wm_param[DC__NUM_PIPES__MAX];
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struct vba_vars_st vba;
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struct dal_logger *logger;
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};
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@ -25,13 +25,55 @@
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#ifndef __DISPLAY_MODE_STRUCTS_H__
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#define __DISPLAY_MODE_STRUCTS_H__
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typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
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typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
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typedef struct _vcs_dpi_mode_evaluation_st mode_evaluation_st;
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typedef struct _vcs_dpi_ip_params_st ip_params_st;
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typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
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typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
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typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st;
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typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
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typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
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typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
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typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
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typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
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typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
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typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st;
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typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st;
|
||||
typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st;
|
||||
typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st;
|
||||
typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st;
|
||||
typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
|
||||
typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
|
||||
typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
|
||||
typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st;
|
||||
typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
|
||||
typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
|
||||
typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
|
||||
typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
|
||||
typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
|
||||
typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
|
||||
typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
|
||||
typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
|
||||
typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
|
||||
typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st;
|
||||
typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st;
|
||||
typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
|
||||
|
||||
struct _vcs_dpi_mode_evaluation_st {
|
||||
int voltage_override;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_voltage_scaling_st {
|
||||
int state;
|
||||
double dcfclk_mhz;
|
||||
double socclk_mhz;
|
||||
double dram_speed_mhz;
|
||||
double fabricclk_mhz;
|
||||
double dispclk_mhz;
|
||||
double dppclk_mhz;
|
||||
double dram_bw_per_chan_gbps;
|
||||
double phyclk_mhz;
|
||||
double socclk_mhz;
|
||||
double dppclk_mhz;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_soc_bounding_box_st {
|
||||
@ -49,6 +91,10 @@ struct _vcs_dpi_soc_bounding_box_st {
|
||||
double dram_page_open_time_ns;
|
||||
double dram_rw_turnaround_time_ns;
|
||||
double dram_return_buffer_per_channel_bytes;
|
||||
double dram_channel_width_bytes;
|
||||
double fabric_datapath_to_dcn_data_return_bytes;
|
||||
double dcn_downspread_percent;
|
||||
double dispclk_dppclk_vco_speed_mhz;
|
||||
unsigned int round_trip_ping_latency_dcfclk_cycles;
|
||||
unsigned int urgent_out_of_order_return_per_channel_bytes;
|
||||
unsigned int channel_interleave_bytes;
|
||||
@ -58,12 +104,19 @@ struct _vcs_dpi_soc_bounding_box_st {
|
||||
double dram_clock_change_latency_us;
|
||||
double writeback_dram_clock_change_latency_us;
|
||||
unsigned int return_bus_width_bytes;
|
||||
double xfc_bus_transport_time_us;
|
||||
double xfc_xbuf_latency_tolerance_us;
|
||||
struct _vcs_dpi_voltage_scaling_st clock_limits[7];
|
||||
};
|
||||
|
||||
struct _vcs_dpi_ip_params_st {
|
||||
unsigned int max_inter_dcn_tile_repeaters;
|
||||
unsigned int num_dsc;
|
||||
unsigned int odm_capable;
|
||||
unsigned int rob_buffer_size_kbytes;
|
||||
unsigned int det_buffer_size_kbytes;
|
||||
unsigned int dpte_buffer_size_in_pte_reqs;
|
||||
unsigned int pde_proc_buffer_size_64k_reqs;
|
||||
unsigned int dpp_output_buffer_pixels;
|
||||
unsigned int opp_output_buffer_lines;
|
||||
unsigned int pixel_chunk_size_kbytes;
|
||||
@ -73,10 +126,10 @@ struct _vcs_dpi_ip_params_st {
|
||||
unsigned int writeback_chunk_size_kbytes;
|
||||
unsigned int line_buffer_size_bits;
|
||||
unsigned int max_line_buffer_lines;
|
||||
unsigned int IsLineBufferBppFixed;
|
||||
unsigned int LineBufferFixedBpp;
|
||||
unsigned int writeback_luma_buffer_size_kbytes;
|
||||
unsigned int writeback_chroma_buffer_size_kbytes;
|
||||
unsigned int writeback_chroma_line_buffer_width_pixels;
|
||||
unsigned int max_page_table_levels;
|
||||
unsigned int max_num_dpp;
|
||||
unsigned int max_num_wb;
|
||||
unsigned int max_dchub_pscl_bw_pix_per_clk;
|
||||
@ -89,28 +142,54 @@ struct _vcs_dpi_ip_params_st {
|
||||
unsigned int vscl_mults;
|
||||
unsigned int max_hscl_taps;
|
||||
unsigned int max_vscl_taps;
|
||||
unsigned int xfc_supported;
|
||||
unsigned int ptoi_supported;
|
||||
unsigned int xfc_fill_constant_bytes;
|
||||
double dispclk_ramp_margin_percent;
|
||||
double xfc_fill_bw_overhead_percent;
|
||||
double underscan_factor;
|
||||
unsigned int min_vblank_lines;
|
||||
unsigned int dppclk_delay_subtotal;
|
||||
unsigned int dispclk_delay_subtotal;
|
||||
unsigned int dcfclk_cstate_latency;
|
||||
unsigned int max_inter_dcn_tile_repeaters;
|
||||
unsigned int dppclk_delay_scl;
|
||||
unsigned int dppclk_delay_scl_lb_only;
|
||||
unsigned int dppclk_delay_cnvc_formatter;
|
||||
unsigned int dppclk_delay_cnvc_cursor;
|
||||
unsigned int is_line_buffer_bpp_fixed;
|
||||
unsigned int line_buffer_fixed_bpp;
|
||||
unsigned int dcc_supported;
|
||||
|
||||
unsigned int IsLineBufferBppFixed;
|
||||
unsigned int LineBufferFixedBpp;
|
||||
unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
|
||||
unsigned int bug_forcing_LC_req_same_size_fixed;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_xfc_params_st {
|
||||
double xfc_tslv_vready_offset_us;
|
||||
double xfc_tslv_vupdate_width_us;
|
||||
double xfc_tslv_vupdate_offset_us;
|
||||
int xfc_slv_chunk_size_bytes;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_pipe_source_params_st {
|
||||
int source_format;
|
||||
unsigned char dcc;
|
||||
unsigned int dcc_override;
|
||||
unsigned int dcc_rate;
|
||||
unsigned char dcc_use_global;
|
||||
unsigned char vm;
|
||||
unsigned char vm_levels_force_en;
|
||||
unsigned int vm_levels_force;
|
||||
int source_scan;
|
||||
int sw_mode;
|
||||
int macro_tile_size;
|
||||
unsigned char is_display_sw;
|
||||
unsigned int viewport_width;
|
||||
unsigned int viewport_height;
|
||||
unsigned int viewport_y_y;
|
||||
unsigned int viewport_y_c;
|
||||
unsigned int viewport_width_c;
|
||||
unsigned int viewport_height_c;
|
||||
unsigned int data_pitch;
|
||||
@ -119,15 +198,41 @@ struct _vcs_dpi_display_pipe_source_params_st {
|
||||
unsigned int meta_pitch_c;
|
||||
unsigned int cur0_src_width;
|
||||
int cur0_bpp;
|
||||
unsigned int cur1_src_width;
|
||||
int cur1_bpp;
|
||||
int num_cursors;
|
||||
unsigned char is_hsplit;
|
||||
unsigned char dynamic_metadata_enable;
|
||||
unsigned int dynamic_metadata_lines_before_active;
|
||||
unsigned int dynamic_metadata_xmit_bytes;
|
||||
unsigned int hsplit_grp;
|
||||
unsigned char xfc_enable;
|
||||
unsigned char xfc_slave;
|
||||
struct _vcs_dpi_display_xfc_params_st xfc_params;
|
||||
};
|
||||
struct writeback_st {
|
||||
int wb_src_height;
|
||||
int wb_dst_width;
|
||||
int wb_dst_height;
|
||||
int wb_pixel_format;
|
||||
int wb_htaps_luma;
|
||||
int wb_vtaps_luma;
|
||||
int wb_htaps_chroma;
|
||||
int wb_vtaps_chroma;
|
||||
int wb_hratio;
|
||||
int wb_vratio;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_output_params_st {
|
||||
int output_bpp;
|
||||
int dsc_enable;
|
||||
int wb_enable;
|
||||
int output_bpc;
|
||||
int output_type;
|
||||
int output_format;
|
||||
int output_standard;
|
||||
int dsc_slices;
|
||||
struct writeback_st wb;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_bandwidth_st {
|
||||
@ -145,6 +250,7 @@ struct _vcs_dpi_scaler_ratio_depth_st {
|
||||
double vinit_bot;
|
||||
double vinit_bot_c;
|
||||
int lb_depth;
|
||||
int scl_enable;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_scaler_taps_st {
|
||||
@ -166,22 +272,25 @@ struct _vcs_dpi_display_pipe_dest_params_st {
|
||||
unsigned int htotal;
|
||||
unsigned int vtotal;
|
||||
unsigned int vactive;
|
||||
unsigned int hactive;
|
||||
unsigned int vstartup_start;
|
||||
unsigned int vupdate_offset;
|
||||
unsigned int vupdate_width;
|
||||
unsigned int vready_offset;
|
||||
unsigned int vsync_plus_back_porch;
|
||||
unsigned char interlaced;
|
||||
unsigned char underscan;
|
||||
double pixel_rate_mhz;
|
||||
unsigned char syncronized_vblank_all_planes;
|
||||
unsigned char synchronized_vblank_all_planes;
|
||||
unsigned char otg_inst;
|
||||
unsigned char odm_split_cnt;
|
||||
unsigned char odm_combine;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_pipe_params_st {
|
||||
struct _vcs_dpi_display_pipe_source_params_st src;
|
||||
struct _vcs_dpi_display_pipe_dest_params_st dest;
|
||||
struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth;
|
||||
struct _vcs_dpi_scaler_taps_st scale_taps;
|
||||
display_pipe_source_params_st src;
|
||||
display_pipe_dest_params_st dest;
|
||||
scaler_ratio_depth_st scale_ratio_depth;
|
||||
scaler_taps_st scale_taps;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_clocks_and_cfg_st {
|
||||
@ -194,9 +303,9 @@ struct _vcs_dpi_display_clocks_and_cfg_st {
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st {
|
||||
struct _vcs_dpi_display_pipe_params_st pipe;
|
||||
struct _vcs_dpi_display_output_params_st dout;
|
||||
struct _vcs_dpi_display_clocks_and_cfg_st clks_cfg;
|
||||
display_pipe_params_st pipe;
|
||||
display_output_params_st dout;
|
||||
display_clocks_and_cfg_st clks_cfg;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_dchub_buffer_sizing_st {
|
||||
@ -298,27 +407,27 @@ struct _vcs_dpi_display_cur_rq_dlg_params_st {
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_rq_dlg_params_st {
|
||||
struct _vcs_dpi_display_data_rq_dlg_params_st rq_l;
|
||||
struct _vcs_dpi_display_data_rq_dlg_params_st rq_c;
|
||||
struct _vcs_dpi_display_cur_rq_dlg_params_st rq_cur0;
|
||||
display_data_rq_dlg_params_st rq_l;
|
||||
display_data_rq_dlg_params_st rq_c;
|
||||
display_cur_rq_dlg_params_st rq_cur0;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_rq_sizing_params_st {
|
||||
struct _vcs_dpi_display_data_rq_sizing_params_st rq_l;
|
||||
struct _vcs_dpi_display_data_rq_sizing_params_st rq_c;
|
||||
display_data_rq_sizing_params_st rq_l;
|
||||
display_data_rq_sizing_params_st rq_c;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_rq_misc_params_st {
|
||||
struct _vcs_dpi_display_data_rq_misc_params_st rq_l;
|
||||
struct _vcs_dpi_display_data_rq_misc_params_st rq_c;
|
||||
display_data_rq_misc_params_st rq_l;
|
||||
display_data_rq_misc_params_st rq_c;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_rq_params_st {
|
||||
unsigned char yuv420;
|
||||
unsigned char yuv420_10bpc;
|
||||
struct _vcs_dpi_display_rq_misc_params_st misc;
|
||||
struct _vcs_dpi_display_rq_sizing_params_st sizing;
|
||||
struct _vcs_dpi_display_rq_dlg_params_st dlg;
|
||||
display_rq_misc_params_st misc;
|
||||
display_rq_sizing_params_st sizing;
|
||||
display_rq_dlg_params_st dlg;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_dlg_regs_st {
|
||||
@ -331,6 +440,8 @@ struct _vcs_dpi_display_dlg_regs_st {
|
||||
unsigned int dst_y_prefetch;
|
||||
unsigned int dst_y_per_vm_vblank;
|
||||
unsigned int dst_y_per_row_vblank;
|
||||
unsigned int dst_y_per_vm_flip;
|
||||
unsigned int dst_y_per_row_flip;
|
||||
unsigned int ref_freq_to_pix_freq;
|
||||
unsigned int vratio_prefetch;
|
||||
unsigned int vratio_prefetch_c;
|
||||
@ -338,6 +449,10 @@ struct _vcs_dpi_display_dlg_regs_st {
|
||||
unsigned int refcyc_per_pte_group_vblank_c;
|
||||
unsigned int refcyc_per_meta_chunk_vblank_l;
|
||||
unsigned int refcyc_per_meta_chunk_vblank_c;
|
||||
unsigned int refcyc_per_pte_group_flip_l;
|
||||
unsigned int refcyc_per_pte_group_flip_c;
|
||||
unsigned int refcyc_per_meta_chunk_flip_l;
|
||||
unsigned int refcyc_per_meta_chunk_flip_c;
|
||||
unsigned int dst_y_per_pte_row_nom_l;
|
||||
unsigned int dst_y_per_pte_row_nom_c;
|
||||
unsigned int refcyc_per_pte_group_nom_l;
|
||||
@ -351,6 +466,15 @@ struct _vcs_dpi_display_dlg_regs_st {
|
||||
unsigned int refcyc_per_line_delivery_l;
|
||||
unsigned int refcyc_per_line_delivery_c;
|
||||
unsigned int chunk_hdl_adjust_cur0;
|
||||
unsigned int chunk_hdl_adjust_cur1;
|
||||
unsigned int vready_after_vcount0;
|
||||
unsigned int dst_y_offset_cur0;
|
||||
unsigned int dst_y_offset_cur1;
|
||||
unsigned int xfc_reg_transfer_delay;
|
||||
unsigned int xfc_reg_precharge_delay;
|
||||
unsigned int xfc_reg_remote_surface_flip_latency;
|
||||
unsigned int xfc_reg_prefetch_margin;
|
||||
unsigned int dst_y_delta_drq_limit;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_ttu_regs_st {
|
||||
@ -361,15 +485,19 @@ struct _vcs_dpi_display_ttu_regs_st {
|
||||
unsigned int refcyc_per_req_delivery_l;
|
||||
unsigned int refcyc_per_req_delivery_c;
|
||||
unsigned int refcyc_per_req_delivery_cur0;
|
||||
unsigned int refcyc_per_req_delivery_cur1;
|
||||
unsigned int refcyc_per_req_delivery_pre_l;
|
||||
unsigned int refcyc_per_req_delivery_pre_c;
|
||||
unsigned int refcyc_per_req_delivery_pre_cur0;
|
||||
unsigned int refcyc_per_req_delivery_pre_cur1;
|
||||
unsigned int qos_level_fixed_l;
|
||||
unsigned int qos_level_fixed_c;
|
||||
unsigned int qos_level_fixed_cur0;
|
||||
unsigned int qos_level_fixed_cur1;
|
||||
unsigned int qos_ramp_disable_l;
|
||||
unsigned int qos_ramp_disable_c;
|
||||
unsigned int qos_ramp_disable_cur0;
|
||||
unsigned int qos_ramp_disable_cur1;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_data_rq_regs_st {
|
||||
@ -384,8 +512,8 @@ struct _vcs_dpi_display_data_rq_regs_st {
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_rq_regs_st {
|
||||
struct _vcs_dpi_display_data_rq_regs_st rq_regs_l;
|
||||
struct _vcs_dpi_display_data_rq_regs_st rq_regs_c;
|
||||
display_data_rq_regs_st rq_regs_l;
|
||||
display_data_rq_regs_st rq_regs_c;
|
||||
unsigned int drq_expansion_mode;
|
||||
unsigned int prq_expansion_mode;
|
||||
unsigned int mrq_expansion_mode;
|
||||
@ -398,6 +526,7 @@ struct _vcs_dpi_display_dlg_sys_params_st {
|
||||
double t_urg_wm_us;
|
||||
double t_sr_wm_us;
|
||||
double t_extra_us;
|
||||
double mem_trip_us;
|
||||
double t_srx_delay_us;
|
||||
double deepsleep_dcfclk_mhz;
|
||||
double total_flip_bw;
|
||||
@ -412,8 +541,9 @@ struct _vcs_dpi_display_dlg_prefetch_param_st {
|
||||
struct _vcs_dpi_display_pipe_clock_st {
|
||||
double dcfclk_mhz;
|
||||
double dispclk_mhz;
|
||||
double dppclk_mhz[4];
|
||||
unsigned char dppclk_div[4];
|
||||
double socclk_mhz;
|
||||
double dscclk_mhz[6];
|
||||
double dppclk_mhz[6];
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_arb_params_st {
|
||||
@ -422,8 +552,4 @@ struct _vcs_dpi_display_arb_params_st {
|
||||
int sat_level_us;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_mode_evaluation_st {
|
||||
int voltage_override;
|
||||
};
|
||||
|
||||
#endif /*__DISPLAY_MODE_STRUCTS_H__*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,199 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
#ifndef __DISPLAY_MODE_SUPPORT_H__
|
||||
#define __DISPLAY_MODE_SUPPORT_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
#define NumberOfStates 4
|
||||
#define NumberOfStatesPlusTwo (NumberOfStates+2)
|
||||
|
||||
struct dml_ms_internal_vars {
|
||||
double ScaleRatioSupport;
|
||||
double SourceFormatPixelAndScanSupport;
|
||||
double TotalReadBandwidthConsumedGBytePerSecond;
|
||||
double TotalWriteBandwidthConsumedGBytePerSecond;
|
||||
double TotalBandwidthConsumedGBytePerSecond;
|
||||
double DCCEnabledInAnyPlane;
|
||||
double ReturnBWToDCNPerState;
|
||||
double CriticalPoint;
|
||||
double WritebackLatencySupport;
|
||||
double RequiredOutputBW;
|
||||
double TotalNumberOfActiveWriteback;
|
||||
double TotalAvailableWritebackSupport;
|
||||
double MaximumSwathWidth;
|
||||
double NumberOfDPPRequiredForDETSize;
|
||||
double NumberOfDPPRequiredForLBSize;
|
||||
double MinDispclkUsingSingleDPP;
|
||||
double MinDispclkUsingDualDPP;
|
||||
double ViewportSizeSupport;
|
||||
double SwathWidthGranularityY;
|
||||
double RoundedUpMaxSwathSizeBytesY;
|
||||
double SwathWidthGranularityC;
|
||||
double RoundedUpMaxSwathSizeBytesC;
|
||||
double LinesInDETLuma;
|
||||
double LinesInDETChroma;
|
||||
double EffectiveLBLatencyHidingSourceLinesLuma;
|
||||
double EffectiveLBLatencyHidingSourceLinesChroma;
|
||||
double EffectiveDETLBLinesLuma;
|
||||
double EffectiveDETLBLinesChroma;
|
||||
double ProjectedDCFCLKDeepSleep;
|
||||
double MetaReqHeightY;
|
||||
double MetaReqWidthY;
|
||||
double MetaSurfaceWidthY;
|
||||
double MetaSurfaceHeightY;
|
||||
double MetaPteBytesPerFrameY;
|
||||
double MetaRowBytesY;
|
||||
double MacroTileBlockSizeBytesY;
|
||||
double MacroTileBlockHeightY;
|
||||
double DataPTEReqHeightY;
|
||||
double DataPTEReqWidthY;
|
||||
double DPTEBytesPerRowY;
|
||||
double MetaReqHeightC;
|
||||
double MetaReqWidthC;
|
||||
double MetaSurfaceWidthC;
|
||||
double MetaSurfaceHeightC;
|
||||
double MetaPteBytesPerFrameC;
|
||||
double MetaRowBytesC;
|
||||
double MacroTileBlockSizeBytesC;
|
||||
double MacroTileBlockHeightC;
|
||||
double MacroTileBlockWidthC;
|
||||
double DataPTEReqHeightC;
|
||||
double DataPTEReqWidthC;
|
||||
double DPTEBytesPerRowC;
|
||||
double VInitY;
|
||||
double MaxPartialSwY;
|
||||
double VInitC;
|
||||
double MaxPartialSwC;
|
||||
double dst_x_after_scaler;
|
||||
double dst_y_after_scaler;
|
||||
double TimeCalc;
|
||||
double VUpdateOffset;
|
||||
double TotalRepeaterDelay;
|
||||
double VUpdateWidth;
|
||||
double VReadyOffset;
|
||||
double TimeSetup;
|
||||
double ExtraLatency;
|
||||
double MaximumVStartup;
|
||||
double BWAvailableForImmediateFlip;
|
||||
double TotalImmediateFlipBytes;
|
||||
double TimeForMetaPTEWithImmediateFlip;
|
||||
double TimeForMetaPTEWithoutImmediateFlip;
|
||||
double TimeForMetaAndDPTERowWithImmediateFlip;
|
||||
double TimeForMetaAndDPTERowWithoutImmediateFlip;
|
||||
double LineTimesToRequestPrefetchPixelDataWithImmediateFlip;
|
||||
double LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip;
|
||||
double MaximumReadBandwidthWithPrefetchWithImmediateFlip;
|
||||
double MaximumReadBandwidthWithPrefetchWithoutImmediateFlip;
|
||||
double VoltageOverrideLevel;
|
||||
double VoltageLevelWithImmediateFlip;
|
||||
double VoltageLevelWithoutImmediateFlip;
|
||||
double ImmediateFlipSupported;
|
||||
double VoltageLevel;
|
||||
double DCFCLK;
|
||||
double FabricAndDRAMBandwidth;
|
||||
double SwathWidthYSingleDPP[DC__NUM_PIPES__MAX];
|
||||
double BytePerPixelInDETY[DC__NUM_PIPES__MAX];
|
||||
double BytePerPixelInDETC[DC__NUM_PIPES__MAX];
|
||||
double ReadBandwidth[DC__NUM_PIPES__MAX];
|
||||
double WriteBandwidth[DC__NUM_PIPES__MAX];
|
||||
double DCFCLKPerState[NumberOfStatesPlusTwo];
|
||||
double FabricAndDRAMBandwidthPerState[NumberOfStatesPlusTwo];
|
||||
double ReturnBWPerState[NumberOfStatesPlusTwo];
|
||||
double BandwidthSupport[NumberOfStatesPlusTwo];
|
||||
double UrgentRoundTripAndOutOfOrderLatencyPerState[NumberOfStatesPlusTwo];
|
||||
double ROBSupport[NumberOfStatesPlusTwo];
|
||||
double RequiredPHYCLK[DC__NUM_PIPES__MAX];
|
||||
double DIOSupport[NumberOfStatesPlusTwo];
|
||||
double PHYCLKPerState[NumberOfStatesPlusTwo];
|
||||
double PSCL_FACTOR[DC__NUM_PIPES__MAX];
|
||||
double PSCL_FACTOR_CHROMA[DC__NUM_PIPES__MAX];
|
||||
double MinDPPCLKUsingSingleDPP[DC__NUM_PIPES__MAX];
|
||||
double Read256BlockHeightY[DC__NUM_PIPES__MAX];
|
||||
double Read256BlockWidthY[DC__NUM_PIPES__MAX];
|
||||
double Read256BlockHeightC[DC__NUM_PIPES__MAX];
|
||||
double Read256BlockWidthC[DC__NUM_PIPES__MAX];
|
||||
double MaxSwathHeightY[DC__NUM_PIPES__MAX];
|
||||
double MaxSwathHeightC[DC__NUM_PIPES__MAX];
|
||||
double MinSwathHeightY[DC__NUM_PIPES__MAX];
|
||||
double MinSwathHeightC[DC__NUM_PIPES__MAX];
|
||||
double NumberOfDPPRequiredForDETAndLBSize[DC__NUM_PIPES__MAX];
|
||||
double TotalNumberOfActiveDPP[NumberOfStatesPlusTwo * 2];
|
||||
double RequiredDISPCLK[NumberOfStatesPlusTwo * 2];
|
||||
double DISPCLK_DPPCLK_Support[NumberOfStatesPlusTwo * 2];
|
||||
double MaxDispclk[NumberOfStatesPlusTwo];
|
||||
double MaxDppclk[NumberOfStatesPlusTwo];
|
||||
double NoOfDPP[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double TotalAvailablePipesSupport[NumberOfStatesPlusTwo * 2];
|
||||
double SwathWidthYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double SwathHeightYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double SwathHeightCPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double DETBufferSizeYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double UrgentLatencySupportUsPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double UrgentLatencySupport[NumberOfStatesPlusTwo * 2];
|
||||
double TotalNumberOfDCCActiveDPP[NumberOfStatesPlusTwo * 2];
|
||||
double DPTEBytesPerRow[DC__NUM_PIPES__MAX];
|
||||
double MetaPTEBytesPerFrame[DC__NUM_PIPES__MAX];
|
||||
double MetaRowBytes[DC__NUM_PIPES__MAX];
|
||||
double PrefillY[DC__NUM_PIPES__MAX];
|
||||
double MaxNumSwY[DC__NUM_PIPES__MAX];
|
||||
double PrefetchLinesY[DC__NUM_PIPES__MAX];
|
||||
double PrefillC[DC__NUM_PIPES__MAX];
|
||||
double MaxNumSwC[DC__NUM_PIPES__MAX];
|
||||
double PrefetchLinesC[DC__NUM_PIPES__MAX];
|
||||
double LineTimesForPrefetch[DC__NUM_PIPES__MAX];
|
||||
double PrefetchBW[DC__NUM_PIPES__MAX];
|
||||
double LinesForMetaPTEWithImmediateFlip[DC__NUM_PIPES__MAX];
|
||||
double LinesForMetaPTEWithoutImmediateFlip[DC__NUM_PIPES__MAX];
|
||||
double LinesForMetaAndDPTERowWithImmediateFlip[DC__NUM_PIPES__MAX];
|
||||
double LinesForMetaAndDPTERowWithoutImmediateFlip[DC__NUM_PIPES__MAX];
|
||||
double VRatioPreYWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double VRatioPreCWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double RequiredPrefetchPixelDataBWWithImmediateFlip[NumberOfStatesPlusTwo * 2
|
||||
* DC__NUM_PIPES__MAX];
|
||||
double VRatioPreYWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double VRatioPreCWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
|
||||
double RequiredPrefetchPixelDataBWWithoutImmediateFlip[NumberOfStatesPlusTwo * 2
|
||||
* DC__NUM_PIPES__MAX];
|
||||
double PrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
|
||||
double PrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
|
||||
double VRatioInPrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
|
||||
double VRatioInPrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
|
||||
double ModeSupportWithImmediateFlip[NumberOfStatesPlusTwo * 2];
|
||||
double ModeSupportWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
|
||||
double RequiredDISPCLKPerRatio[2];
|
||||
double DPPPerPlanePerRatio[2 * DC__NUM_PIPES__MAX];
|
||||
double DISPCLK_DPPCLK_SupportPerRatio[2];
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st planes[DC__NUM_PIPES__MAX];
|
||||
};
|
||||
|
||||
int dml_ms_check(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
int num_pipes);
|
||||
|
||||
#endif
|
||||
3263
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
Normal file
3263
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
Normal file
File diff suppressed because it is too large
Load Diff
410
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
Normal file
410
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
Normal file
@ -0,0 +1,410 @@
|
||||
/*
|
||||
* display_mode_vba.h
|
||||
*
|
||||
* Created on: Aug 18, 2017
|
||||
* Author: dlaktyus
|
||||
*/
|
||||
|
||||
#ifndef __DML2_DISPLAY_MODE_VBA_H__
|
||||
#define __DML2_DISPLAY_MODE_VBA_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
void set_prefetch_mode(struct display_mode_lib *mode_lib,
|
||||
bool cstate_en,
|
||||
bool pstate_en,
|
||||
bool ignore_viewport_pos,
|
||||
bool immediate_flip_support);
|
||||
|
||||
#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
|
||||
|
||||
dml_get_attr_decl(clk_dcf_deepsleep);
|
||||
dml_get_attr_decl(wm_urgent);
|
||||
dml_get_attr_decl(wm_memory_trip);
|
||||
dml_get_attr_decl(wm_writeback_urgent);
|
||||
dml_get_attr_decl(wm_stutter_exit);
|
||||
dml_get_attr_decl(wm_stutter_enter_exit);
|
||||
dml_get_attr_decl(wm_dram_clock_change);
|
||||
dml_get_attr_decl(wm_writeback_dram_clock_change);
|
||||
dml_get_attr_decl(wm_xfc_underflow);
|
||||
dml_get_attr_decl(stutter_efficiency_no_vblank);
|
||||
dml_get_attr_decl(stutter_efficiency);
|
||||
dml_get_attr_decl(urgent_latency);
|
||||
dml_get_attr_decl(urgent_extra_latency);
|
||||
dml_get_attr_decl(nonurgent_latency);
|
||||
dml_get_attr_decl(dram_clock_change_latency);
|
||||
dml_get_attr_decl(dispclk_calculated);
|
||||
dml_get_attr_decl(total_data_read_bw);
|
||||
dml_get_attr_decl(return_bw);
|
||||
dml_get_attr_decl(tcalc);
|
||||
|
||||
#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
|
||||
|
||||
dml_get_pipe_attr_decl(dsc_delay);
|
||||
dml_get_pipe_attr_decl(dppclk_calculated);
|
||||
dml_get_pipe_attr_decl(dscclk_calculated);
|
||||
dml_get_pipe_attr_decl(min_ttu_vblank);
|
||||
dml_get_pipe_attr_decl(vratio_prefetch_l);
|
||||
dml_get_pipe_attr_decl(vratio_prefetch_c);
|
||||
dml_get_pipe_attr_decl(dst_x_after_scaler);
|
||||
dml_get_pipe_attr_decl(dst_y_after_scaler);
|
||||
dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
|
||||
dml_get_pipe_attr_decl(dst_y_per_row_vblank);
|
||||
dml_get_pipe_attr_decl(dst_y_prefetch);
|
||||
dml_get_pipe_attr_decl(dst_y_per_vm_flip);
|
||||
dml_get_pipe_attr_decl(dst_y_per_row_flip);
|
||||
dml_get_pipe_attr_decl(xfc_transfer_delay);
|
||||
dml_get_pipe_attr_decl(xfc_precharge_delay);
|
||||
dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
|
||||
dml_get_pipe_attr_decl(xfc_prefetch_margin);
|
||||
|
||||
unsigned int get_vstartup_calculated(
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes,
|
||||
unsigned int which_pipe);
|
||||
|
||||
double get_total_immediate_flip_bytes(
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
double get_total_immediate_flip_bw(
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
double get_total_prefetch_bw(
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
|
||||
bool Calculate256BBlockSizes(
|
||||
enum source_format_class SourcePixelFormat,
|
||||
enum dm_swizzle_mode SurfaceTiling,
|
||||
unsigned int BytePerPixelY,
|
||||
unsigned int BytePerPixelC,
|
||||
unsigned int *BlockHeight256BytesY,
|
||||
unsigned int *BlockHeight256BytesC,
|
||||
unsigned int *BlockWidth256BytesY,
|
||||
unsigned int *BlockWidth256BytesC);
|
||||
|
||||
|
||||
struct vba_vars_st {
|
||||
ip_params_st ip;
|
||||
soc_bounding_box_st soc;
|
||||
mode_evaluation_st me;
|
||||
|
||||
unsigned int MaximumMaxVStartupLines;
|
||||
double cursor_bw[DC__NUM_PIPES__MAX];
|
||||
double meta_row_bw[DC__NUM_PIPES__MAX];
|
||||
double dpte_row_bw[DC__NUM_PIPES__MAX];
|
||||
double qual_row_bw[DC__NUM_PIPES__MAX];
|
||||
double WritebackDISPCLK;
|
||||
double PSCL_THROUGHPUT_LUMA[DC__NUM_PIPES__MAX];
|
||||
double PSCL_THROUGHPUT_CHROMA[DC__NUM_PIPES__MAX];
|
||||
double DPPCLKUsingSingleDPPLuma;
|
||||
double DPPCLKUsingSingleDPPChroma;
|
||||
double DPPCLKUsingSingleDPP[DC__NUM_PIPES__MAX];
|
||||
double DISPCLKWithRamping;
|
||||
double DISPCLKWithoutRamping;
|
||||
double GlobalDPPCLK;
|
||||
double MaxDispclk;
|
||||
double DISPCLKWithRampingRoundedToDFSGranularity;
|
||||
double DISPCLKWithoutRampingRoundedToDFSGranularity;
|
||||
double MaxDispclkRoundedToDFSGranularity;
|
||||
bool DCCEnabledAnyPlane;
|
||||
double ReturnBandwidthToDCN;
|
||||
unsigned int SwathWidthY[DC__NUM_PIPES__MAX];
|
||||
unsigned int SwathWidthSingleDPPY[DC__NUM_PIPES__MAX];
|
||||
double BytePerPixelDETY[DC__NUM_PIPES__MAX];
|
||||
double BytePerPixelDETC[DC__NUM_PIPES__MAX];
|
||||
double ReadBandwidthPlaneLuma[DC__NUM_PIPES__MAX];
|
||||
double ReadBandwidthPlaneChroma[DC__NUM_PIPES__MAX];
|
||||
unsigned int TotalActiveDPP;
|
||||
unsigned int TotalDCCActiveDPP;
|
||||
double UrgentRoundTripAndOutOfOrderLatency;
|
||||
double DisplayPipeLineDeliveryTimeLuma[DC__NUM_PIPES__MAX]; // WM
|
||||
double DisplayPipeLineDeliveryTimeChroma[DC__NUM_PIPES__MAX]; // WM
|
||||
double LinesInDETY[DC__NUM_PIPES__MAX]; // WM
|
||||
double LinesInDETC[DC__NUM_PIPES__MAX]; // WM
|
||||
unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_PIPES__MAX]; // WM
|
||||
unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_PIPES__MAX]; // WM
|
||||
double FullDETBufferingTimeY[DC__NUM_PIPES__MAX]; // WM
|
||||
double FullDETBufferingTimeC[DC__NUM_PIPES__MAX]; // WM
|
||||
double MinFullDETBufferingTime;
|
||||
double FrameTimeForMinFullDETBufferingTime;
|
||||
double AverageReadBandwidthGBytePerSecond;
|
||||
double PartOfBurstThatFitsInROB;
|
||||
double StutterBurstTime;
|
||||
//unsigned int NextPrefetchMode;
|
||||
double VBlankTime;
|
||||
double SmallestVBlank;
|
||||
double DCFCLKDeepSleepPerPlane;
|
||||
double EffectiveDETPlusLBLinesLuma;
|
||||
double EffectiveDETPlusLBLinesChroma;
|
||||
double UrgentLatencySupportUsLuma;
|
||||
double UrgentLatencySupportUsChroma;
|
||||
double UrgentLatencySupportUs[DC__NUM_PIPES__MAX];
|
||||
unsigned int DSCFormatFactor;
|
||||
unsigned int BlockHeight256BytesY[DC__NUM_PIPES__MAX];
|
||||
unsigned int BlockHeight256BytesC[DC__NUM_PIPES__MAX];
|
||||
unsigned int BlockWidth256BytesY[DC__NUM_PIPES__MAX];
|
||||
unsigned int BlockWidth256BytesC[DC__NUM_PIPES__MAX];
|
||||
double VInitPreFillY[DC__NUM_PIPES__MAX];
|
||||
double VInitPreFillC[DC__NUM_PIPES__MAX];
|
||||
unsigned int MaxNumSwathY[DC__NUM_PIPES__MAX];
|
||||
unsigned int MaxNumSwathC[DC__NUM_PIPES__MAX];
|
||||
double PrefetchSourceLinesY[DC__NUM_PIPES__MAX];
|
||||
double PrefetchSourceLinesC[DC__NUM_PIPES__MAX];
|
||||
double PixelPTEBytesPerRow[DC__NUM_PIPES__MAX];
|
||||
double MetaRowByte[DC__NUM_PIPES__MAX];
|
||||
bool PTEBufferSizeNotExceeded; // not used
|
||||
unsigned int dpte_row_height[DC__NUM_PIPES__MAX];
|
||||
unsigned int dpte_row_height_chroma[DC__NUM_PIPES__MAX];
|
||||
unsigned int meta_row_height[DC__NUM_PIPES__MAX];
|
||||
unsigned int meta_row_height_chroma[DC__NUM_PIPES__MAX];
|
||||
|
||||
unsigned int MacroTileWidthY;
|
||||
unsigned int MacroTileWidthC;
|
||||
unsigned int MaxVStartupLines[DC__NUM_PIPES__MAX];
|
||||
double WritebackDelay[DC__NUM_PIPES__MAX];
|
||||
bool PrefetchModeSupported;
|
||||
bool AllowDRAMClockChangeDuringVBlank[DC__NUM_PIPES__MAX];
|
||||
bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_PIPES__MAX];
|
||||
double RequiredPrefetchPixDataBW[DC__NUM_PIPES__MAX];
|
||||
double XFCRemoteSurfaceFlipDelay;
|
||||
double TInitXFill;
|
||||
double TslvChk;
|
||||
double SrcActiveDrainRate;
|
||||
double Tno_bw[DC__NUM_PIPES__MAX];
|
||||
bool ImmediateFlipSupported;
|
||||
|
||||
double prefetch_vm_bw[DC__NUM_PIPES__MAX];
|
||||
double prefetch_row_bw[DC__NUM_PIPES__MAX];
|
||||
bool ImmediateFlipSupportedForPipe[DC__NUM_PIPES__MAX];
|
||||
unsigned int VStartupLines;
|
||||
double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_PIPES__MAX];
|
||||
double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_PIPES__MAX];
|
||||
unsigned int ActiveDPPs;
|
||||
unsigned int LBLatencyHidingSourceLinesY;
|
||||
unsigned int LBLatencyHidingSourceLinesC;
|
||||
double ActiveDRAMClockChangeLatencyMargin[DC__NUM_PIPES__MAX];
|
||||
double MinActiveDRAMClockChangeMargin;
|
||||
double XFCSlaveVUpdateOffset[DC__NUM_PIPES__MAX];
|
||||
double XFCSlaveVupdateWidth[DC__NUM_PIPES__MAX];
|
||||
double XFCSlaveVReadyOffset[DC__NUM_PIPES__MAX];
|
||||
double InitFillLevel;
|
||||
double FinalFillMargin;
|
||||
double FinalFillLevel;
|
||||
double RemainingFillLevel;
|
||||
double TFinalxFill;
|
||||
|
||||
|
||||
//
|
||||
// SOC Bounding Box Parameters
|
||||
//
|
||||
double SRExitTime;
|
||||
double SREnterPlusExitTime;
|
||||
double UrgentLatency;
|
||||
double WritebackLatency;
|
||||
double PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency;
|
||||
double NumberOfChannels;
|
||||
double DRAMChannelWidth;
|
||||
double FabricDatapathToDCNDataReturn;
|
||||
double ReturnBusWidth;
|
||||
double Downspreading;
|
||||
double DISPCLKDPPCLKDSCCLKDownSpreading;
|
||||
double DISPCLKDPPCLKVCOSpeed;
|
||||
double RoundTripPingLatencyCycles;
|
||||
double UrgentOutOfOrderReturnPerChannel;
|
||||
unsigned int VMMPageSize;
|
||||
double DRAMClockChangeLatency;
|
||||
double XFCBusTransportTime;
|
||||
double XFCXBUFLatencyTolerance;
|
||||
|
||||
//
|
||||
// IP Parameters
|
||||
//
|
||||
unsigned int ROBBufferSizeInKByte;
|
||||
double DETBufferSizeInKByte;
|
||||
unsigned int DPPOutputBufferPixels;
|
||||
unsigned int OPPOutputBufferLines;
|
||||
unsigned int PixelChunkSizeInKByte;
|
||||
double ReturnBW;
|
||||
bool VirtualMemoryEnable;
|
||||
unsigned int MaxPageTableLevels;
|
||||
unsigned int OverridePageTableLevels;
|
||||
unsigned int PTEChunkSize;
|
||||
unsigned int MetaChunkSize;
|
||||
unsigned int WritebackChunkSize;
|
||||
bool ODMCapability;
|
||||
unsigned int NumberOfDSC;
|
||||
unsigned int LineBufferSize;
|
||||
unsigned int MaxLineBufferLines;
|
||||
unsigned int WritebackInterfaceLumaBufferSize;
|
||||
unsigned int WritebackInterfaceChromaBufferSize;
|
||||
unsigned int WritebackChromaLineBufferWidth;
|
||||
double MaxDCHUBToPSCLThroughput;
|
||||
double MaxPSCLToLBThroughput;
|
||||
unsigned int PTEBufferSizeInRequests;
|
||||
double DISPCLKRampingMargin;
|
||||
unsigned int MaxInterDCNTileRepeaters;
|
||||
bool XFCSupported;
|
||||
double XFCSlvChunkSize;
|
||||
double XFCFillBWOverhead;
|
||||
double XFCFillConstant;
|
||||
double XFCTSlvVupdateOffset;
|
||||
double XFCTSlvVupdateWidth;
|
||||
double XFCTSlvVreadyOffset;
|
||||
double DPPCLKDelaySubtotal;
|
||||
double DPPCLKDelaySCL;
|
||||
double DPPCLKDelaySCLLBOnly;
|
||||
double DPPCLKDelayCNVCFormater;
|
||||
double DPPCLKDelayCNVCCursor;
|
||||
double DISPCLKDelaySubtotal;
|
||||
bool ProgressiveToInterlaceUnitInOPP;
|
||||
unsigned int PDEProcessingBufIn64KBReqs;
|
||||
|
||||
// Pipe/Plane Parameters
|
||||
int VoltageLevel;
|
||||
double FabricAndDRAMBandwidth;
|
||||
double FabricClock;
|
||||
double DRAMSpeed;
|
||||
double DISPCLK;
|
||||
double SOCCLK;
|
||||
double DCFCLK;
|
||||
|
||||
unsigned int NumberOfActivePlanes;
|
||||
unsigned int ViewportWidth[DC__NUM_DPP];
|
||||
unsigned int ViewportHeight[DC__NUM_DPP];
|
||||
unsigned int ViewportYStartY[DC__NUM_DPP];
|
||||
unsigned int ViewportYStartC[DC__NUM_DPP];
|
||||
unsigned int PitchY[DC__NUM_DPP];
|
||||
unsigned int PitchC[DC__NUM_DPP];
|
||||
double HRatio[DC__NUM_DPP];
|
||||
double VRatio[DC__NUM_DPP];
|
||||
unsigned int htaps[DC__NUM_DPP];
|
||||
unsigned int vtaps[DC__NUM_DPP];
|
||||
unsigned int HTAPsChroma[DC__NUM_DPP];
|
||||
unsigned int VTAPsChroma[DC__NUM_DPP];
|
||||
unsigned int HTotal[DC__NUM_DPP];
|
||||
unsigned int VTotal[DC__NUM_DPP];
|
||||
unsigned int DPPPerPlane[DC__NUM_DPP];
|
||||
double PixelClock[DC__NUM_DPP];
|
||||
double PixelClockBackEnd[DC__NUM_DPP];
|
||||
double DPPCLK[DC__NUM_DPP];
|
||||
bool DCCEnable[DC__NUM_DPP];
|
||||
unsigned int DCCMetaPitchY[DC__NUM_DPP];
|
||||
enum scan_direction_class SourceScan[DC__NUM_DPP];
|
||||
enum source_format_class SourcePixelFormat[DC__NUM_DPP];
|
||||
bool WritebackEnable[DC__NUM_DPP];
|
||||
double WritebackDestinationWidth[DC__NUM_DPP];
|
||||
double WritebackDestinationHeight[DC__NUM_DPP];
|
||||
double WritebackSourceHeight[DC__NUM_DPP];
|
||||
enum source_format_class WritebackPixelFormat[DC__NUM_DPP];
|
||||
unsigned int WritebackLumaHTaps[DC__NUM_DPP];
|
||||
unsigned int WritebackLumaVTaps[DC__NUM_DPP];
|
||||
unsigned int WritebackChromaHTaps[DC__NUM_DPP];
|
||||
unsigned int WritebackChromaVTaps[DC__NUM_DPP];
|
||||
double WritebackHRatio[DC__NUM_DPP];
|
||||
double WritebackVRatio[DC__NUM_DPP];
|
||||
unsigned int HActive[DC__NUM_DPP];
|
||||
unsigned int VActive[DC__NUM_DPP];
|
||||
bool Interlace[DC__NUM_DPP];
|
||||
enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP];
|
||||
unsigned int ScalerRecoutWidth[DC__NUM_DPP];
|
||||
bool DynamicMetadataEnable[DC__NUM_DPP];
|
||||
unsigned int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP];
|
||||
unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP];
|
||||
double DCCRate[DC__NUM_DPP];
|
||||
bool ODMCombineEnabled[DC__NUM_DPP];
|
||||
double OutputBpp[DC__NUM_DPP];
|
||||
unsigned int NumberOfDSCSlices[DC__NUM_DPP];
|
||||
bool DSCEnabled[DC__NUM_DPP];
|
||||
unsigned int DSCDelay[DC__NUM_DPP];
|
||||
unsigned int DSCInputBitPerComponent[DC__NUM_DPP];
|
||||
enum output_format_class OutputFormat[DC__NUM_DPP];
|
||||
enum output_encoder_class Output[DC__NUM_DPP];
|
||||
unsigned int BlendingAndTiming[DC__NUM_DPP];
|
||||
bool SynchronizedVBlank;
|
||||
unsigned int NumberOfCursors[DC__NUM_DPP];
|
||||
unsigned int CursorWidth[DC__NUM_DPP][DC__NUM_CURSOR];
|
||||
unsigned int CursorBPP[DC__NUM_DPP][DC__NUM_CURSOR];
|
||||
bool XFCEnabled[DC__NUM_DPP];
|
||||
bool ScalerEnabled[DC__NUM_DPP];
|
||||
|
||||
// Intermediates/Informational
|
||||
bool ImmediateFlipSupport;
|
||||
unsigned int SwathHeightY[DC__NUM_DPP];
|
||||
unsigned int SwathHeightC[DC__NUM_DPP];
|
||||
unsigned int DETBufferSizeY[DC__NUM_DPP];
|
||||
unsigned int DETBufferSizeC[DC__NUM_DPP];
|
||||
unsigned int LBBitPerPixel[DC__NUM_DPP];
|
||||
double LastPixelOfLineExtraWatermark;
|
||||
double TotalDataReadBandwidth;
|
||||
unsigned int TotalActiveWriteback;
|
||||
unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
|
||||
unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
|
||||
double BandwidthAvailableForImmediateFlip;
|
||||
unsigned int PrefetchMode;
|
||||
bool IgnoreViewportPositioning;
|
||||
double PrefetchBandwidth[DC__NUM_DPP];
|
||||
bool ErrorResult[DC__NUM_DPP];
|
||||
double PDEAndMetaPTEBytesFrame[DC__NUM_DPP];
|
||||
|
||||
//
|
||||
// Calculated dml_ml->vba.Outputs
|
||||
//
|
||||
double DCFClkDeepSleep;
|
||||
double UrgentWatermark;
|
||||
double UrgentExtraLatency;
|
||||
double MemoryTripWatermark;
|
||||
double WritebackUrgentWatermark;
|
||||
double StutterExitWatermark;
|
||||
double StutterEnterPlusExitWatermark;
|
||||
double DRAMClockChangeWatermark;
|
||||
double WritebackDRAMClockChangeWatermark;
|
||||
double StutterEfficiency;
|
||||
double StutterEfficiencyNotIncludingVBlank;
|
||||
double MinUrgentLatencySupportUs;
|
||||
double NonUrgentLatencyTolerance;
|
||||
double MinActiveDRAMClockChangeLatencySupported;
|
||||
enum clock_change_support DRAMClockChangeSupport;
|
||||
|
||||
// These are the clocks calcuated by the library but they are not actually
|
||||
// used explicitly. They are fetched by tests and then possibly used. The
|
||||
// ultimate values to use are the ones specified by the parameters to DML
|
||||
double DISPCLK_calculated;
|
||||
double DSCCLK_calculated[DC__NUM_DPP];
|
||||
double DPPCLK_calculated[DC__NUM_DPP];
|
||||
|
||||
unsigned int VStartup[DC__NUM_DPP];
|
||||
unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
|
||||
|
||||
double ImmediateFlipBW;
|
||||
unsigned int TotImmediateFlipBytes;
|
||||
double TCalc;
|
||||
double MinTTUVBlank[DC__NUM_DPP];
|
||||
double VRatioPrefetchY[DC__NUM_DPP];
|
||||
double VRatioPrefetchC[DC__NUM_DPP];
|
||||
double DSTXAfterScaler[DC__NUM_DPP];
|
||||
double DSTYAfterScaler[DC__NUM_DPP];
|
||||
|
||||
double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP];
|
||||
double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP];
|
||||
double DestinationLinesForPrefetch[DC__NUM_DPP];
|
||||
double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP];
|
||||
double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP];
|
||||
|
||||
double XFCTransferDelay[DC__NUM_DPP];
|
||||
double XFCPrechargeDelay[DC__NUM_DPP];
|
||||
double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP];
|
||||
double XFCPrefetchMargin[DC__NUM_DPP];
|
||||
|
||||
display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP];
|
||||
unsigned int cache_num_pipes;
|
||||
unsigned int pipe_plane[DC__NUM_PIPES__MAX];
|
||||
};
|
||||
|
||||
#endif /* _DML2_DISPLAY_MODE_VBA_H_ */
|
||||
@ -27,340 +27,79 @@
|
||||
#include "display_mode_lib.h"
|
||||
#include "soc_bounding_box.h"
|
||||
|
||||
static enum voltage_state power_state(
|
||||
display_pipe_clock_st dml_clks_get_pipe_clocks(
|
||||
struct display_mode_lib *mode_lib,
|
||||
double dispclk,
|
||||
double dppclk)
|
||||
{
|
||||
enum voltage_state state1;
|
||||
enum voltage_state state2;
|
||||
|
||||
if (dispclk <= mode_lib->soc.vmin.dispclk_mhz)
|
||||
state1 = dm_vmin;
|
||||
else if (dispclk <= mode_lib->soc.vnom.dispclk_mhz)
|
||||
state1 = dm_vnom;
|
||||
else if (dispclk <= mode_lib->soc.vmax.dispclk_mhz)
|
||||
state1 = dm_vmax;
|
||||
else
|
||||
state1 = dm_vmax_exceeded;
|
||||
|
||||
if (dppclk <= mode_lib->soc.vmin.dppclk_mhz)
|
||||
state2 = dm_vmin;
|
||||
else if (dppclk <= mode_lib->soc.vnom.dppclk_mhz)
|
||||
state2 = dm_vnom;
|
||||
else if (dppclk <= mode_lib->soc.vmax.dppclk_mhz)
|
||||
state2 = dm_vmax;
|
||||
else
|
||||
state2 = dm_vmax_exceeded;
|
||||
|
||||
if (state1 > state2)
|
||||
return state1;
|
||||
else
|
||||
return state2;
|
||||
}
|
||||
|
||||
static unsigned int dpp_in_grp(
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes,
|
||||
unsigned int hsplit_grp)
|
||||
{
|
||||
unsigned int num_dpp = 0;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num_pipes; i++) {
|
||||
if (e2e[i].pipe.src.is_hsplit) {
|
||||
if (e2e[i].pipe.src.hsplit_grp == hsplit_grp) {
|
||||
num_dpp++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (0 == num_dpp)
|
||||
num_dpp = 1;
|
||||
|
||||
return num_dpp;
|
||||
}
|
||||
|
||||
static void calculate_pipe_clk_requirement(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_dpp_in_grp,
|
||||
double *dppclk,
|
||||
double *dispclk,
|
||||
bool *dppdiv)
|
||||
{
|
||||
double pscl_throughput = 0.0;
|
||||
double max_hratio = e2e->pipe.scale_ratio_depth.hscl_ratio;
|
||||
double max_vratio = e2e->pipe.scale_ratio_depth.vscl_ratio;
|
||||
double max_htaps = e2e->pipe.scale_taps.htaps;
|
||||
double max_vtaps = e2e->pipe.scale_taps.vtaps;
|
||||
double dpp_clock_divider = (double) num_dpp_in_grp;
|
||||
double dispclk_dppclk_ratio;
|
||||
double dispclk_ramp_margin_percent;
|
||||
|
||||
if (max_hratio > 1.0) {
|
||||
double pscl_to_lb = ((double) mode_lib->ip.max_pscl_lb_bw_pix_per_clk * max_hratio)
|
||||
/ dml_ceil(max_htaps / 6.0);
|
||||
pscl_throughput = dml_min(
|
||||
pscl_to_lb,
|
||||
(double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk);
|
||||
} else {
|
||||
pscl_throughput = dml_min(
|
||||
(double) mode_lib->ip.max_pscl_lb_bw_pix_per_clk,
|
||||
(double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk);
|
||||
}
|
||||
|
||||
DTRACE("pscl_throughput: %f pix per clk", pscl_throughput);
|
||||
DTRACE("vtaps: %f hratio: %f vratio: %f", max_vtaps, max_hratio, max_vratio);
|
||||
*dppclk = dml_max(
|
||||
max_vtaps / 6.0 * dml_min(1.0, max_hratio),
|
||||
max_hratio * max_vratio / pscl_throughput);
|
||||
DTRACE("pixel rate multiplier: %f", *dppclk);
|
||||
*dppclk = dml_max(*dppclk, 1.0);
|
||||
DTRACE("pixel rate multiplier clamped: %f", *dppclk);
|
||||
*dppclk = *dppclk * e2e->pipe.dest.pixel_rate_mhz;
|
||||
|
||||
*dppclk = *dppclk / dpp_clock_divider;
|
||||
DTRACE("dppclk after split: %f", *dppclk);
|
||||
|
||||
if (dpp_clock_divider > 1.0 && (*dppclk < e2e->pipe.dest.pixel_rate_mhz)) {
|
||||
dispclk_dppclk_ratio = 2.0;
|
||||
*dppdiv = true;
|
||||
} else {
|
||||
dispclk_dppclk_ratio = 1.0;
|
||||
*dppdiv = false;
|
||||
}
|
||||
|
||||
dispclk_ramp_margin_percent = mode_lib->ip.dispclk_ramp_margin_percent;
|
||||
|
||||
/* Comment this out because of Gabes possible bug in spreadsheet,
|
||||
* just to make other cases evident during debug
|
||||
*
|
||||
*if(e2e->clks_cfg.voltage == dm_vmax)
|
||||
* dispclk_ramp_margin_percent = 0.0;
|
||||
*/
|
||||
|
||||
/* account for ramping margin and downspread */
|
||||
*dispclk = dml_max(*dppclk * dispclk_dppclk_ratio, e2e->pipe.dest.pixel_rate_mhz)
|
||||
* (1.0 + (double) mode_lib->soc.downspread_percent / 100.0)
|
||||
* (1.0 + (double) dispclk_ramp_margin_percent / 100.0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
bool dml_clks_pipe_clock_requirement_fit_power_constraint(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_dpp_in_grp)
|
||||
{
|
||||
double dppclk = 0;
|
||||
double dispclk = 0;
|
||||
bool dppdiv = 0;
|
||||
|
||||
calculate_pipe_clk_requirement(mode_lib, e2e, num_dpp_in_grp, &dppclk, &dispclk, &dppdiv);
|
||||
|
||||
if (power_state(mode_lib, dispclk, dppclk) > e2e->clks_cfg.voltage) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void get_plane_clks(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes,
|
||||
double *dppclks,
|
||||
double *dispclks,
|
||||
bool *dppdiv)
|
||||
{
|
||||
/* it is assumed that the scale ratios passed into the e2e pipe params have already been calculated
|
||||
* for any split pipe configurations, where extra pixels inthe overlap region do not contribute to
|
||||
* the scale ratio. This means that we can simply calculate the dppclk for each dpp independently
|
||||
* and we would expect the same result on any split pipes, which would be handled
|
||||
*/
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num_pipes; i++) {
|
||||
double num_dpp_in_grp;
|
||||
double dispclk_ramp_margin_percent;
|
||||
double dispclk_margined;
|
||||
|
||||
if (e2e[i].pipe.src.is_hsplit)
|
||||
num_dpp_in_grp = (double) dpp_in_grp(
|
||||
e2e,
|
||||
num_pipes,
|
||||
e2e[i].pipe.src.hsplit_grp);
|
||||
else
|
||||
num_dpp_in_grp = 1;
|
||||
|
||||
calculate_pipe_clk_requirement(
|
||||
mode_lib,
|
||||
&e2e[i],
|
||||
num_dpp_in_grp,
|
||||
&dppclks[i],
|
||||
&dispclks[i],
|
||||
&dppdiv[i]);
|
||||
|
||||
dispclk_ramp_margin_percent = mode_lib->ip.dispclk_ramp_margin_percent;
|
||||
|
||||
dispclk_margined = e2e[i].pipe.dest.pixel_rate_mhz
|
||||
* (1.0 + (double) mode_lib->soc.downspread_percent / 100.0)
|
||||
* (1.0 + (double) dispclk_ramp_margin_percent / 100.0);
|
||||
|
||||
DTRACE("p%d: requested power state: %d", i, (int) e2e[0].clks_cfg.voltage);
|
||||
|
||||
if (power_state(mode_lib, dispclks[i], dppclks[i])
|
||||
> power_state(mode_lib, dispclk_margined, dispclk_margined)
|
||||
&& dispclk_margined > dppclks[i]) {
|
||||
if (power_state(mode_lib, dispclks[i], dppclks[i])
|
||||
> e2e[0].clks_cfg.voltage) {
|
||||
dispclks[i] = dispclk_margined;
|
||||
dppclks[i] = dispclk_margined;
|
||||
dppdiv[i] = false;
|
||||
}
|
||||
}
|
||||
|
||||
DTRACE("p%d: dispclk: %f", i, dispclks[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static void get_dcfclk(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes,
|
||||
double *dcfclk_mhz)
|
||||
{
|
||||
double bytes_per_pixel_det_y[DC__NUM_PIPES__MAX];
|
||||
double bytes_per_pixel_det_c[DC__NUM_PIPES__MAX];
|
||||
double swath_width_y[DC__NUM_PIPES__MAX];
|
||||
unsigned int i;
|
||||
double total_read_bandwidth_gbps = 0.0;
|
||||
|
||||
for (i = 0; i < num_pipes; i++) {
|
||||
if (e2e[i].pipe.src.source_scan == dm_horz) {
|
||||
swath_width_y[i] = e2e[i].pipe.src.viewport_width * 1.0;
|
||||
} else {
|
||||
swath_width_y[i] = e2e[i].pipe.src.viewport_height * 1.0;
|
||||
}
|
||||
|
||||
switch (e2e[i].pipe.src.source_format) {
|
||||
case dm_444_64:
|
||||
bytes_per_pixel_det_y[i] = 8.0;
|
||||
bytes_per_pixel_det_c[i] = 0.0;
|
||||
break;
|
||||
case dm_444_32:
|
||||
bytes_per_pixel_det_y[i] = 4.0;
|
||||
bytes_per_pixel_det_c[i] = 0.0;
|
||||
break;
|
||||
case dm_444_16:
|
||||
bytes_per_pixel_det_y[i] = 2.0;
|
||||
bytes_per_pixel_det_c[i] = 0.0;
|
||||
break;
|
||||
case dm_422_8:
|
||||
bytes_per_pixel_det_y[i] = 2.0;
|
||||
bytes_per_pixel_det_c[i] = 0.0;
|
||||
break;
|
||||
case dm_422_10:
|
||||
bytes_per_pixel_det_y[i] = 4.0;
|
||||
bytes_per_pixel_det_c[i] = 0.0;
|
||||
break;
|
||||
case dm_420_8:
|
||||
bytes_per_pixel_det_y[i] = 1.0;
|
||||
bytes_per_pixel_det_c[i] = 2.0;
|
||||
break;
|
||||
case dm_420_10:
|
||||
bytes_per_pixel_det_y[i] = 4.0 / 3.0;
|
||||
bytes_per_pixel_det_c[i] = 8.0 / 3.0;
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER(); /* invalid src_format in get_dcfclk */
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < num_pipes; i++) {
|
||||
double read_bandwidth_plane_mbps = 0.0;
|
||||
read_bandwidth_plane_mbps = (double) swath_width_y[i]
|
||||
* ((double) bytes_per_pixel_det_y[i]
|
||||
+ (double) bytes_per_pixel_det_c[i] / 2.0)
|
||||
/ ((double) e2e[i].pipe.dest.htotal
|
||||
/ (double) e2e[i].pipe.dest.pixel_rate_mhz)
|
||||
* e2e[i].pipe.scale_ratio_depth.vscl_ratio;
|
||||
|
||||
if (e2e[i].pipe.src.dcc) {
|
||||
read_bandwidth_plane_mbps += (read_bandwidth_plane_mbps / 1000.0 / 256.0);
|
||||
}
|
||||
|
||||
if (e2e[i].pipe.src.vm) {
|
||||
read_bandwidth_plane_mbps += (read_bandwidth_plane_mbps / 1000.0 / 512.0);
|
||||
}
|
||||
|
||||
total_read_bandwidth_gbps = total_read_bandwidth_gbps
|
||||
+ read_bandwidth_plane_mbps / 1000.0;
|
||||
}
|
||||
|
||||
DTRACE("total bandwidth = %f gbps", total_read_bandwidth_gbps);
|
||||
|
||||
(*dcfclk_mhz) = (total_read_bandwidth_gbps * 1000.0) / mode_lib->soc.return_bus_width_bytes;
|
||||
|
||||
DTRACE(
|
||||
"minimum theoretical dcfclk without stutter and full utilization = %f MHz",
|
||||
(*dcfclk_mhz));
|
||||
|
||||
}
|
||||
|
||||
struct _vcs_dpi_display_pipe_clock_st dml_clks_get_pipe_clocks(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes)
|
||||
{
|
||||
struct _vcs_dpi_display_pipe_clock_st clocks;
|
||||
double max_dispclk = 0.0;
|
||||
double dcfclk;
|
||||
double dispclks[DC__NUM_PIPES__MAX];
|
||||
double dppclks[DC__NUM_PIPES__MAX];
|
||||
bool dppdiv[DC__NUM_PIPES__MAX];
|
||||
unsigned int i;
|
||||
display_pipe_clock_st clocks;
|
||||
bool visited[DC__NUM_PIPES__MAX];
|
||||
double max_dispclk = 25.0; //the min dispclk is 25MHz, so keep the min dispclk caculated larger thant 25MHz
|
||||
double dcfclk, socclk;
|
||||
unsigned int i, j, k;
|
||||
unsigned int dsc_inst = 0;
|
||||
|
||||
DTRACE("Calculating pipe clocks...");
|
||||
|
||||
/* this is the theoretical minimum, have to adjust based on valid values for soc */
|
||||
get_dcfclk(mode_lib, e2e, num_pipes, &dcfclk);
|
||||
|
||||
/* if(dcfclk > soc.vnom.dcfclk_mhz)
|
||||
* dcfclk = soc.vmax.dcfclk_mhz;
|
||||
* else if(dcfclk > soc.vmin.dcfclk_mhz)
|
||||
* dcfclk = soc.vnom.dcfclk_mhz;
|
||||
* else
|
||||
* dcfclk = soc.vmin.dcfclk_mhz;
|
||||
*/
|
||||
|
||||
dcfclk = dml_socbb_voltage_scaling(
|
||||
&mode_lib->soc,
|
||||
(enum voltage_state) e2e[0].clks_cfg.voltage).dcfclk_mhz;
|
||||
socclk = dml_socbb_voltage_scaling(
|
||||
&mode_lib->soc,
|
||||
(enum voltage_state) e2e[0].clks_cfg.voltage).socclk_mhz;
|
||||
clocks.dcfclk_mhz = dcfclk;
|
||||
clocks.socclk_mhz = socclk;
|
||||
|
||||
get_plane_clks(mode_lib, e2e, num_pipes, dppclks, dispclks, dppdiv);
|
||||
|
||||
for (i = 0; i < num_pipes; i++) {
|
||||
max_dispclk = dml_max(max_dispclk, dispclks[i]);
|
||||
}
|
||||
|
||||
max_dispclk = dml_max(max_dispclk, get_dispclk_calculated(mode_lib, e2e, num_pipes));
|
||||
clocks.dispclk_mhz = max_dispclk;
|
||||
DTRACE(" dispclk: %f Mhz", clocks.dispclk_mhz);
|
||||
DTRACE(" dcfclk: %f Mhz", clocks.dcfclk_mhz);
|
||||
DTRACE(" socclk: %f Mhz", clocks.socclk_mhz);
|
||||
|
||||
for (k = 0; k < num_pipes; ++k)
|
||||
visited[k] = false;
|
||||
|
||||
for (i = 0; i < num_pipes; i++) {
|
||||
if (dppclks[i] * 2 < max_dispclk)
|
||||
dppdiv[i] = 1;
|
||||
|
||||
if (dppdiv[i])
|
||||
clocks.dppclk_div[i] = 1;
|
||||
else
|
||||
clocks.dppclk_div[i] = 0;
|
||||
|
||||
clocks.dppclk_mhz[i] = max_dispclk / ((dppdiv[i]) ? 2.0 : 1.0);
|
||||
clocks.dppclk_mhz[i] = get_dppclk_calculated(mode_lib, e2e, num_pipes, i);
|
||||
DTRACE(" dppclk%d: %f Mhz", i, clocks.dppclk_mhz[i]);
|
||||
|
||||
if (e2e[i].pipe.src.is_hsplit && !visited[i]) {
|
||||
unsigned int grp = e2e[i].pipe.src.hsplit_grp;
|
||||
|
||||
for (j = i; j < num_pipes; j++) {
|
||||
if (e2e[j].pipe.src.hsplit_grp == grp && e2e[j].pipe.src.is_hsplit
|
||||
&& !visited[j]) {
|
||||
clocks.dscclk_mhz[j] = get_dscclk_calculated(
|
||||
mode_lib,
|
||||
e2e,
|
||||
num_pipes,
|
||||
dsc_inst);
|
||||
DTRACE(" dscclk%d: %f Mhz", j, clocks.dscclk_mhz[j]);
|
||||
visited[j] = true;
|
||||
}
|
||||
}
|
||||
dsc_inst++;
|
||||
}
|
||||
|
||||
if (!visited[i]) {
|
||||
unsigned int otg_inst = e2e[i].pipe.dest.otg_inst;
|
||||
|
||||
for (j = i; j < num_pipes; j++) {
|
||||
// assign dscclk to all planes with this otg, except if they're doing odm combine, or mpc combine
|
||||
// which is handled by the conditions above, the odm_combine is not required, but it helps make sense of this code
|
||||
if (e2e[j].pipe.dest.otg_inst == otg_inst
|
||||
&& !e2e[j].pipe.dest.odm_combine && !visited[j]) {
|
||||
clocks.dscclk_mhz[j] = get_dscclk_calculated(
|
||||
mode_lib,
|
||||
e2e,
|
||||
num_pipes,
|
||||
dsc_inst);
|
||||
DTRACE(" dscclk%d: %f Mhz", j, clocks.dscclk_mhz[j]);
|
||||
visited[j] = true;
|
||||
}
|
||||
}
|
||||
dsc_inst++;
|
||||
}
|
||||
}
|
||||
|
||||
return clocks;
|
||||
|
||||
@ -29,13 +29,9 @@
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
struct _vcs_dpi_display_pipe_clock_st dml_clks_get_pipe_clocks(
|
||||
display_pipe_clock_st dml_clks_get_pipe_clocks(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes);
|
||||
|
||||
bool dml_clks_pipe_clock_requirement_fit_power_constraint(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_dpp_in_grp);
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -22,103 +22,114 @@
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
#ifndef __DISPLAY_RQ_DLG_CALC_H__
|
||||
#define __DISPLAY_RQ_DLG_CALC_H__
|
||||
|
||||
#ifndef __DML2_DISPLAY_RQ_DLG_CALC_H__
|
||||
#define __DML2_DISPLAY_RQ_DLG_CALC_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
#include "display_rq_dlg_helpers.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
void extract_rq_regs(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
||||
const struct _vcs_dpi_display_rq_params_st rq_param);
|
||||
/* Function: dml_rq_dlg_get_rq_params
|
||||
* Calculate requestor related parameters that register definition agnostic
|
||||
* (i.e. this layer does try to separate real values from register defintion)
|
||||
* Input:
|
||||
* pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
* Output:
|
||||
* rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
|
||||
*/
|
||||
// Function: dml_rq_dlg_get_rq_params
|
||||
// Calculate requestor related parameters that register definition agnostic
|
||||
// (i.e. this layer does try to separate real values from register definition)
|
||||
// Input:
|
||||
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
// Output:
|
||||
// rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
|
||||
//
|
||||
void dml_rq_dlg_get_rq_params(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_params_st *rq_param,
|
||||
const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
|
||||
display_rq_params_st *rq_param,
|
||||
const display_pipe_source_params_st pipe_src_param);
|
||||
|
||||
/* Function: dml_rq_dlg_get_rq_reg
|
||||
* Main entry point for test to get the register values out of this DML class.
|
||||
* This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
|
||||
* and then populate the rq_regs struct
|
||||
* Input:
|
||||
* pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
* Output:
|
||||
* rq_regs - struct that holds all the RQ registers field value.
|
||||
* See also: <display_rq_regs_st>
|
||||
*/
|
||||
// Function: dml_rq_dlg_get_rq_reg
|
||||
// Main entry point for test to get the register values out of this DML class.
|
||||
// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
|
||||
// and then populate the rq_regs struct
|
||||
// Input:
|
||||
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
// Output:
|
||||
// rq_regs - struct that holds all the RQ registers field value.
|
||||
// See also: <display_rq_regs_st>
|
||||
void dml_rq_dlg_get_rq_reg(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
||||
const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
|
||||
display_rq_regs_st *rq_regs,
|
||||
const display_pipe_source_params_st pipe_src_param);
|
||||
|
||||
/* Function: dml_rq_dlg_get_dlg_params
|
||||
* Calculate deadline related parameters
|
||||
*/
|
||||
void dml_rq_dlg_get_dlg_params(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
|
||||
const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
|
||||
const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
|
||||
const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
|
||||
// Function: dml_rq_dlg_get_dlg_params
|
||||
// Calculate deadline related parameters
|
||||
//
|
||||
void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx,
|
||||
display_dlg_regs_st *disp_dlg_regs,
|
||||
display_ttu_regs_st *disp_ttu_regs,
|
||||
const display_rq_dlg_params_st rq_dlg_param,
|
||||
const display_dlg_sys_params_st dlg_sys_param,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en,
|
||||
const bool iflip_en);
|
||||
const bool ignore_viewport_pos,
|
||||
const bool immediate_flip_support);
|
||||
|
||||
/* Function: dml_rq_dlg_get_dlg_param_prefetch
|
||||
* For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
|
||||
* for ALL pipes and use this info to calculate the prefetch programming.
|
||||
* Output: prefetch_param.prefetch_bw and flip_bytes
|
||||
*/
|
||||
// Function: dml_rq_dlg_get_dlg_param_prefetch
|
||||
// For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
|
||||
// for ALL pipes and use this info to calculate the prefetch programming.
|
||||
// Output: prefetch_param.prefetch_bw and flip_bytes
|
||||
void dml_rq_dlg_get_dlg_params_prefetch(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_prefetch_param_st *prefetch_param,
|
||||
struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
|
||||
struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
|
||||
display_dlg_prefetch_param_st *prefetch_param,
|
||||
display_rq_dlg_params_st rq_dlg_param,
|
||||
display_dlg_sys_params_st dlg_sys_param,
|
||||
display_e2e_pipe_params_st e2e_pipe_param,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en);
|
||||
|
||||
/* Function: dml_rq_dlg_get_dlg_reg
|
||||
* Calculate and return DLG and TTU register struct given the system setting
|
||||
* Output:
|
||||
* dlg_regs - output DLG register struct
|
||||
* ttu_regs - output DLG TTU register struct
|
||||
* Input:
|
||||
* e2e_pipe_param - "compacted" array of e2e pipe param struct
|
||||
* num_pipes - num of active "pipe" or "route"
|
||||
* pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
|
||||
* cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
|
||||
* Added for legacy or unrealistic timing tests.
|
||||
*/
|
||||
// Function: dml_rq_dlg_get_dlg_reg
|
||||
// Calculate and return DLG and TTU register struct given the system setting
|
||||
// Output:
|
||||
// dlg_regs - output DLG register struct
|
||||
// ttu_regs - output DLG TTU register struct
|
||||
// Input:
|
||||
// e2e_pipe_param - "compacted" array of e2e pipe param struct
|
||||
// num_pipes - num of active "pipe" or "route"
|
||||
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
|
||||
// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
|
||||
// Added for legacy or unrealistic timing tests.
|
||||
void dml_rq_dlg_get_dlg_reg(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
display_dlg_regs_st *dlg_regs,
|
||||
display_ttu_regs_st *ttu_regs,
|
||||
display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en,
|
||||
const bool iflip_en);
|
||||
const bool ignore_viewport_pos,
|
||||
const bool immediate_flip_support);
|
||||
|
||||
/* Function: dml_rq_dlg_get_row_heights
|
||||
* Calculate dpte and meta row heights
|
||||
*/
|
||||
// Function: dml_rq_dlg_get_calculated_vstartup
|
||||
// Calculate and return vstartup
|
||||
// Output:
|
||||
// unsigned int vstartup
|
||||
// Input:
|
||||
// e2e_pipe_param - "compacted" array of e2e pipe param struct
|
||||
// num_pipes - num of active "pipe" or "route"
|
||||
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
|
||||
// NOTE: this MUST be called after setting the prefetch mode!
|
||||
unsigned int dml_rq_dlg_get_calculated_vstartup(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx);
|
||||
|
||||
// Function: dml_rq_dlg_get_row_heights
|
||||
// Calculate dpte and meta row heights
|
||||
void dml_rq_dlg_get_row_heights(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int *o_dpte_row_height,
|
||||
@ -131,9 +142,7 @@ void dml_rq_dlg_get_row_heights(
|
||||
int source_scan,
|
||||
int is_chroma);
|
||||
|
||||
/* Function: dml_rq_dlg_get_arb_params */
|
||||
void dml_rq_dlg_get_arb_params(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_arb_params_st *arb_param);
|
||||
// Function: dml_rq_dlg_get_arb_params
|
||||
void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param);
|
||||
|
||||
#endif
|
||||
|
||||
@ -25,296 +25,368 @@
|
||||
|
||||
#include "display_rq_dlg_helpers.h"
|
||||
|
||||
void print__rq_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_params_st rq_param)
|
||||
void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: *************************** ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST");
|
||||
DTRACE("RQ_DLG_CALC: <LUMA>");
|
||||
dml_print("DML_RQ_DLG_CALC: ***************************\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n");
|
||||
dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
|
||||
print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_l);
|
||||
DTRACE("RQ_DLG_CALC: <CHROMA> === ");
|
||||
dml_print("DML_RQ_DLG_CALC: <CHROMA> ===\n");
|
||||
print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_c);
|
||||
|
||||
DTRACE("RQ_DLG_CALC: <LUMA>");
|
||||
dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
|
||||
print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_l);
|
||||
DTRACE("RQ_DLG_CALC: <CHROMA>");
|
||||
dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
|
||||
print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_c);
|
||||
|
||||
DTRACE("RQ_DLG_CALC: <LUMA>");
|
||||
dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
|
||||
print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_l);
|
||||
DTRACE("RQ_DLG_CALC: <CHROMA>");
|
||||
dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
|
||||
print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_c);
|
||||
DTRACE("RQ_DLG_CALC: *************************** ");
|
||||
dml_print("DML_RQ_DLG_CALC: ***************************\n");
|
||||
}
|
||||
|
||||
void print__data_rq_sizing_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing)
|
||||
void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST");
|
||||
DTRACE("RQ_DLG_CALC: chunk_bytes = %0d", rq_sizing.chunk_bytes);
|
||||
DTRACE("RQ_DLG_CALC: min_chunk_bytes = %0d", rq_sizing.min_chunk_bytes);
|
||||
DTRACE("RQ_DLG_CALC: meta_chunk_bytes = %0d", rq_sizing.meta_chunk_bytes);
|
||||
DTRACE("RQ_DLG_CALC: min_meta_chunk_bytes = %0d", rq_sizing.min_meta_chunk_bytes);
|
||||
DTRACE("RQ_DLG_CALC: mpte_group_bytes = %0d", rq_sizing.mpte_group_bytes);
|
||||
DTRACE("RQ_DLG_CALC: dpte_group_bytes = %0d", rq_sizing.dpte_group_bytes);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n");
|
||||
dml_print("DML_RQ_DLG_CALC: chunk_bytes = %0d\n", rq_sizing.chunk_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: min_chunk_bytes = %0d\n", rq_sizing.min_chunk_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: meta_chunk_bytes = %0d\n", rq_sizing.meta_chunk_bytes);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: min_meta_chunk_bytes = %0d\n",
|
||||
rq_sizing.min_meta_chunk_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: mpte_group_bytes = %0d\n", rq_sizing.mpte_group_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: dpte_group_bytes = %0d\n", rq_sizing.dpte_group_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__data_rq_dlg_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_dlg_params_st rq_dlg_param)
|
||||
void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST");
|
||||
DTRACE("RQ_DLG_CALC: swath_width_ub = %0d", rq_dlg_param.swath_width_ub);
|
||||
DTRACE("RQ_DLG_CALC: swath_height = %0d", rq_dlg_param.swath_height);
|
||||
DTRACE("RQ_DLG_CALC: req_per_swath_ub = %0d", rq_dlg_param.req_per_swath_ub);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = %0d",
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n");
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: swath_width_ub = %0d\n",
|
||||
rq_dlg_param.swath_width_ub);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: swath_height = %0d\n",
|
||||
rq_dlg_param.swath_height);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: req_per_swath_ub = %0d\n",
|
||||
rq_dlg_param.req_per_swath_ub);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = %0d\n",
|
||||
rq_dlg_param.meta_pte_bytes_per_frame_ub);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dpte_req_per_row_ub = %0d",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dpte_req_per_row_ub = %0d\n",
|
||||
rq_dlg_param.dpte_req_per_row_ub);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dpte_groups_per_row_ub = %0d",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dpte_groups_per_row_ub = %0d\n",
|
||||
rq_dlg_param.dpte_groups_per_row_ub);
|
||||
DTRACE("RQ_DLG_CALC: dpte_row_height = %0d", rq_dlg_param.dpte_row_height);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dpte_bytes_per_row_ub = %0d",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dpte_row_height = %0d\n",
|
||||
rq_dlg_param.dpte_row_height);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = %0d\n",
|
||||
rq_dlg_param.dpte_bytes_per_row_ub);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: meta_chunks_per_row_ub = %0d",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: meta_chunks_per_row_ub = %0d\n",
|
||||
rq_dlg_param.meta_chunks_per_row_ub);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: meta_req_per_row_ub = %0d",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: meta_req_per_row_ub = %0d\n",
|
||||
rq_dlg_param.meta_req_per_row_ub);
|
||||
DTRACE("RQ_DLG_CALC: meta_row_height = %0d", rq_dlg_param.meta_row_height);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: meta_bytes_per_row_ub = %0d",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: meta_row_height = %0d\n",
|
||||
rq_dlg_param.meta_row_height);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: meta_bytes_per_row_ub = %0d\n",
|
||||
rq_dlg_param.meta_bytes_per_row_ub);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__data_rq_misc_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_misc_params_st rq_misc_param)
|
||||
void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST");
|
||||
DTRACE("RQ_DLG_CALC: full_swath_bytes = %0d", rq_misc_param.full_swath_bytes);
|
||||
DTRACE("RQ_DLG_CALC: stored_swath_bytes = %0d", rq_misc_param.stored_swath_bytes);
|
||||
DTRACE("RQ_DLG_CALC: blk256_width = %0d", rq_misc_param.blk256_width);
|
||||
DTRACE("RQ_DLG_CALC: blk256_height = %0d", rq_misc_param.blk256_height);
|
||||
DTRACE("RQ_DLG_CALC: req_width = %0d", rq_misc_param.req_width);
|
||||
DTRACE("RQ_DLG_CALC: req_height = %0d", rq_misc_param.req_height);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n");
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: full_swath_bytes = %0d\n",
|
||||
rq_misc_param.full_swath_bytes);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: stored_swath_bytes = %0d\n",
|
||||
rq_misc_param.stored_swath_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: blk256_width = %0d\n", rq_misc_param.blk256_width);
|
||||
dml_print("DML_RQ_DLG_CALC: blk256_height = %0d\n", rq_misc_param.blk256_height);
|
||||
dml_print("DML_RQ_DLG_CALC: req_width = %0d\n", rq_misc_param.req_width);
|
||||
dml_print("DML_RQ_DLG_CALC: req_height = %0d\n", rq_misc_param.req_height);
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__rq_dlg_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param)
|
||||
void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST");
|
||||
DTRACE("RQ_DLG_CALC: <LUMA> ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
|
||||
dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
|
||||
print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_l);
|
||||
DTRACE("RQ_DLG_CALC: <CHROMA> ");
|
||||
dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
|
||||
print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_c);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__dlg_sys_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param)
|
||||
void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST");
|
||||
DTRACE("RQ_DLG_CALC: t_mclk_wm_us = %3.2f", dlg_sys_param.t_mclk_wm_us);
|
||||
DTRACE("RQ_DLG_CALC: t_urg_wm_us = %3.2f", dlg_sys_param.t_urg_wm_us);
|
||||
DTRACE("RQ_DLG_CALC: t_sr_wm_us = %3.2f", dlg_sys_param.t_sr_wm_us);
|
||||
DTRACE("RQ_DLG_CALC: t_extra_us = %3.2f", dlg_sys_param.t_extra_us);
|
||||
DTRACE("RQ_DLG_CALC: t_srx_delay_us = %3.2f", dlg_sys_param.t_srx_delay_us);
|
||||
DTRACE("RQ_DLG_CALC: deepsleep_dcfclk_mhz = %3.2f", dlg_sys_param.deepsleep_dcfclk_mhz);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
|
||||
dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param.t_mclk_wm_us);
|
||||
dml_print("DML_RQ_DLG_CALC: t_urg_wm_us = %3.2f\n", dlg_sys_param.t_urg_wm_us);
|
||||
dml_print("DML_RQ_DLG_CALC: t_sr_wm_us = %3.2f\n", dlg_sys_param.t_sr_wm_us);
|
||||
dml_print("DML_RQ_DLG_CALC: t_extra_us = %3.2f\n", dlg_sys_param.t_extra_us);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: t_srx_delay_us = %3.2f\n",
|
||||
dlg_sys_param.t_srx_delay_us);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = %3.2f\n",
|
||||
dlg_sys_param.deepsleep_dcfclk_mhz);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: total_flip_bw = %3.2f\n",
|
||||
dlg_sys_param.total_flip_bw);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: total_flip_bytes = %i\n",
|
||||
dlg_sys_param.total_flip_bytes);
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__data_rq_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_regs_st rq_regs)
|
||||
void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st rq_regs)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST");
|
||||
DTRACE("RQ_DLG_CALC: chunk_size = 0x%0x", rq_regs.chunk_size);
|
||||
DTRACE("RQ_DLG_CALC: min_chunk_size = 0x%0x", rq_regs.min_chunk_size);
|
||||
DTRACE("RQ_DLG_CALC: meta_chunk_size = 0x%0x", rq_regs.meta_chunk_size);
|
||||
DTRACE("RQ_DLG_CALC: min_meta_chunk_size = 0x%0x", rq_regs.min_meta_chunk_size);
|
||||
DTRACE("RQ_DLG_CALC: dpte_group_size = 0x%0x", rq_regs.dpte_group_size);
|
||||
DTRACE("RQ_DLG_CALC: mpte_group_size = 0x%0x", rq_regs.mpte_group_size);
|
||||
DTRACE("RQ_DLG_CALC: swath_height = 0x%0x", rq_regs.swath_height);
|
||||
DTRACE("RQ_DLG_CALC: pte_row_height_linear = 0x%0x", rq_regs.pte_row_height_linear);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n");
|
||||
dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs.chunk_size);
|
||||
dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs.min_chunk_size);
|
||||
dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs.meta_chunk_size);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: min_meta_chunk_size = 0x%0x\n",
|
||||
rq_regs.min_meta_chunk_size);
|
||||
dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs.dpte_group_size);
|
||||
dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs.mpte_group_size);
|
||||
dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs.swath_height);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: pte_row_height_linear = 0x%0x\n",
|
||||
rq_regs.pte_row_height_linear);
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__rq_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_regs_st rq_regs)
|
||||
void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_RQ_REGS_ST");
|
||||
DTRACE("RQ_DLG_CALC: <LUMA> ");
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n");
|
||||
dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
|
||||
print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l);
|
||||
DTRACE("RQ_DLG_CALC: <CHROMA> ");
|
||||
dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
|
||||
print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c);
|
||||
DTRACE("RQ_DLG_CALC: drq_expansion_mode = 0x%0x", rq_regs.drq_expansion_mode);
|
||||
DTRACE("RQ_DLG_CALC: prq_expansion_mode = 0x%0x", rq_regs.prq_expansion_mode);
|
||||
DTRACE("RQ_DLG_CALC: mrq_expansion_mode = 0x%0x", rq_regs.mrq_expansion_mode);
|
||||
DTRACE("RQ_DLG_CALC: crq_expansion_mode = 0x%0x", rq_regs.crq_expansion_mode);
|
||||
DTRACE("RQ_DLG_CALC: plane1_base_address = 0x%0x", rq_regs.plane1_base_address);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print("DML_RQ_DLG_CALC: drq_expansion_mode = 0x%0x\n", rq_regs.drq_expansion_mode);
|
||||
dml_print("DML_RQ_DLG_CALC: prq_expansion_mode = 0x%0x\n", rq_regs.prq_expansion_mode);
|
||||
dml_print("DML_RQ_DLG_CALC: mrq_expansion_mode = 0x%0x\n", rq_regs.mrq_expansion_mode);
|
||||
dml_print("DML_RQ_DLG_CALC: crq_expansion_mode = 0x%0x\n", rq_regs.crq_expansion_mode);
|
||||
dml_print("DML_RQ_DLG_CALC: plane1_base_address = 0x%0x\n", rq_regs.plane1_base_address);
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__dlg_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_regs_st dlg_regs)
|
||||
void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_DLG_REGS_ST ");
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x",
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n");
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x\n",
|
||||
dlg_regs.refcyc_h_blank_end);
|
||||
DTRACE("RQ_DLG_CALC: dlg_vblank_end = 0x%0x", dlg_regs.dlg_vblank_end);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: min_dst_y_next_start = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dlg_vblank_end = 0x%0x\n",
|
||||
dlg_regs.dlg_vblank_end);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: min_dst_y_next_start = 0x%0x\n",
|
||||
dlg_regs.min_dst_y_next_start);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_htotal = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_htotal = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_htotal);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_x_after_scaler = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x%0x\n",
|
||||
dlg_regs.refcyc_x_after_scaler);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_after_scaler = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_after_scaler = 0x%0x\n",
|
||||
dlg_regs.dst_y_after_scaler);
|
||||
DTRACE("RQ_DLG_CALC: dst_y_prefetch = 0x%0x", dlg_regs.dst_y_prefetch);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_per_vm_vblank = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_prefetch = 0x%0x\n",
|
||||
dlg_regs.dst_y_prefetch);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_vm_vblank);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_per_row_vblank = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_row_vblank);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: ref_freq_to_pix_freq = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_vm_flip);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_row_flip);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x%0x\n",
|
||||
dlg_regs.ref_freq_to_pix_freq);
|
||||
DTRACE("RQ_DLG_CALC: vratio_prefetch = 0x%0x", dlg_regs.vratio_prefetch);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: vratio_prefetch_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: vratio_prefetch = 0x%0x\n",
|
||||
dlg_regs.vratio_prefetch);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: vratio_prefetch_c = 0x%0x\n",
|
||||
dlg_regs.vratio_prefetch_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_pte_group_vblank_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_pte_group_vblank_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_meta_chunk_vblank_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_meta_chunk_vblank_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_pte_group_flip_l);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_pte_group_flip_c);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_meta_chunk_flip_l);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_meta_chunk_flip_c);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_pte_row_nom_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_pte_row_nom_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_pte_group_nom_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_pte_group_nom_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_meta_row_nom_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x%0x\n",
|
||||
dlg_regs.dst_y_per_meta_row_nom_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_meta_chunk_nom_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_meta_chunk_nom_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_line_delivery_pre_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_line_delivery_pre_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_line_delivery_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x%0x\n",
|
||||
dlg_regs.refcyc_per_line_delivery_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x\n",
|
||||
dlg_regs.chunk_hdl_adjust_cur0);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x%0x\n",
|
||||
dlg_regs.dst_y_offset_cur1);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x%0x\n",
|
||||
dlg_regs.chunk_hdl_adjust_cur1);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: vready_after_vcount0 = 0x%0x\n",
|
||||
dlg_regs.vready_after_vcount0);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x%0x\n",
|
||||
dlg_regs.dst_y_delta_drq_limit);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x%0x\n",
|
||||
dlg_regs.xfc_reg_transfer_delay);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x%0x\n",
|
||||
dlg_regs.xfc_reg_precharge_delay);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x%0x\n",
|
||||
dlg_regs.xfc_reg_remote_surface_flip_latency);
|
||||
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
void print__ttu_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_ttu_regs_st ttu_regs)
|
||||
void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs)
|
||||
{
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
DTRACE("RQ_DLG_CALC: DISPLAY_TTU_REGS_ST ");
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_level_low_wm = 0x%0x",
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n");
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_low_wm = 0x%0x\n",
|
||||
ttu_regs.qos_level_low_wm);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_level_high_wm = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_high_wm = 0x%0x\n",
|
||||
ttu_regs.qos_level_high_wm);
|
||||
DTRACE("RQ_DLG_CALC: min_ttu_vblank = 0x%0x", ttu_regs.min_ttu_vblank);
|
||||
DTRACE("RQ_DLG_CALC: qos_level_flip = 0x%0x", ttu_regs.qos_level_flip);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: min_ttu_vblank = 0x%0x\n",
|
||||
ttu_regs.min_ttu_vblank);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_flip = 0x%0x\n",
|
||||
ttu_regs.qos_level_flip);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_pre_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_pre_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_cur0);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_pre_cur0);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_level_fixed_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_cur1);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x%0x\n",
|
||||
ttu_regs.refcyc_per_req_delivery_pre_cur1);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_fixed_l = 0x%0x\n",
|
||||
ttu_regs.qos_level_fixed_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_ramp_disable_l = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x%0x\n",
|
||||
ttu_regs.qos_ramp_disable_l);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_level_fixed_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_fixed_c = 0x%0x\n",
|
||||
ttu_regs.qos_level_fixed_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_ramp_disable_c = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x%0x\n",
|
||||
ttu_regs.qos_ramp_disable_c);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_level_fixed_cur0 = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x%0x\n",
|
||||
ttu_regs.qos_level_fixed_cur0);
|
||||
DTRACE(
|
||||
"RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x%0x",
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x%0x\n",
|
||||
ttu_regs.qos_ramp_disable_cur0);
|
||||
DTRACE("RQ_DLG_CALC: ===================================== ");
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x%0x\n",
|
||||
ttu_regs.qos_level_fixed_cur1);
|
||||
dml_print(
|
||||
"DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x%0x\n",
|
||||
ttu_regs.qos_ramp_disable_cur1);
|
||||
dml_print("DML_RQ_DLG_CALC: =====================================\n");
|
||||
}
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DISPLAY_RQ_DLG_HELPERS_H__
|
||||
#define __DISPLAY_RQ_DLG_HELPERS_H__
|
||||
|
||||
@ -31,36 +32,16 @@
|
||||
/* Function: Printer functions
|
||||
* Print various struct
|
||||
*/
|
||||
void print__rq_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_params_st rq_param);
|
||||
void print__data_rq_sizing_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing);
|
||||
void print__data_rq_dlg_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_dlg_params_st rq_dlg_param);
|
||||
void print__data_rq_misc_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_misc_params_st rq_misc_param);
|
||||
void print__rq_dlg_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param);
|
||||
void print__dlg_sys_params_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param);
|
||||
void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param);
|
||||
void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing);
|
||||
void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param);
|
||||
void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param);
|
||||
void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param);
|
||||
void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param);
|
||||
|
||||
void print__data_rq_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_data_rq_regs_st data_rq_regs);
|
||||
void print__rq_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_regs_st rq_regs);
|
||||
void print__dlg_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_regs_st dlg_regs);
|
||||
void print__ttu_regs_st(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_ttu_regs_st ttu_regs);
|
||||
void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st data_rq_regs);
|
||||
void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs);
|
||||
void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs);
|
||||
void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,98 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
#ifndef __DISPLAY_WATERMARK_H__
|
||||
#define __DISPLAY_WATERMARK_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
double dml_wm_urgent_extra(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
double dml_wm_urgent_extra_max(struct display_mode_lib *mode_lib);
|
||||
|
||||
double dml_wm_urgent_e2e(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
double dml_wm_urgent(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
|
||||
unsigned int num_planes);
|
||||
double dml_wm_pte_meta_urgent(struct display_mode_lib *mode_lib, double urgent_wm_us);
|
||||
double dml_wm_dcfclk_deepsleep_mhz_e2e(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
double dml_wm_dcfclk_deepsleep_mhz(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
|
||||
unsigned int num_planes);
|
||||
|
||||
struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate_e2e(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
|
||||
double dml_wm_writeback_pstate_e2e(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
double dml_wm_writeback_pstate(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
|
||||
double dml_wm_expected_stutter_eff_e2e(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes);
|
||||
double dml_wm_expected_stutter_eff_e2e_with_vblank(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes);
|
||||
|
||||
unsigned int dml_wm_e2e_to_wm(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
|
||||
unsigned int num_pipes,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *wm);
|
||||
|
||||
double dml_wm_calc_total_data_read_bw(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
|
||||
unsigned int num_planes);
|
||||
double dml_wm_calc_return_bw(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
|
||||
unsigned int num_planes);
|
||||
|
||||
#endif
|
||||
1903
drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
Normal file
1903
drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DISPLAY_RQ_DLG_CALC_H__
|
||||
#define __DISPLAY_RQ_DLG_CALC_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
#include "display_rq_dlg_helpers.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
void dml1_extract_rq_regs(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
||||
const struct _vcs_dpi_display_rq_params_st rq_param);
|
||||
/* Function: dml_rq_dlg_get_rq_params
|
||||
* Calculate requestor related parameters that register definition agnostic
|
||||
* (i.e. this layer does try to separate real values from register definition)
|
||||
* Input:
|
||||
* pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
* Output:
|
||||
* rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
|
||||
*/
|
||||
void dml1_rq_dlg_get_rq_params(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_params_st *rq_param,
|
||||
const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
|
||||
|
||||
|
||||
/* Function: dml_rq_dlg_get_dlg_params
|
||||
* Calculate deadline related parameters
|
||||
*/
|
||||
void dml1_rq_dlg_get_dlg_params(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
|
||||
const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
|
||||
const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
|
||||
const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en,
|
||||
const bool iflip_en);
|
||||
|
||||
#endif
|
||||
@ -36,21 +36,21 @@ double dml_max(double a, double b)
|
||||
return (double) dcn_bw_max2(a, b);
|
||||
}
|
||||
|
||||
double dml_ceil(double a)
|
||||
double dml_ceil(double a, double granularity)
|
||||
{
|
||||
return (double) dcn_bw_ceil2(a, 1);
|
||||
return (double) dcn_bw_ceil2(a, granularity);
|
||||
}
|
||||
|
||||
double dml_floor(double a)
|
||||
double dml_floor(double a, double granularity)
|
||||
{
|
||||
return (double) dcn_bw_floor2(a, 1);
|
||||
return (double) dcn_bw_floor2(a, granularity);
|
||||
}
|
||||
|
||||
double dml_round(double a)
|
||||
{
|
||||
double round_pt = 0.5;
|
||||
double ceil = dml_ceil(a);
|
||||
double floor = dml_floor(a);
|
||||
double ceil = dml_ceil(a, 1);
|
||||
double floor = dml_floor(a, 1);
|
||||
|
||||
if (a - floor >= round_pt)
|
||||
return ceil;
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_COMMON_DEFS_H__
|
||||
#define __DC_COMMON_DEFS_H__
|
||||
|
||||
@ -30,7 +31,8 @@
|
||||
#include "display_mode_structs.h"
|
||||
#include "display_mode_enums.h"
|
||||
|
||||
#define DTRACE(str, ...) dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__);
|
||||
#define dml_print(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__); }
|
||||
#define DTRACE(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__); }
|
||||
|
||||
double dml_min(double a, double b);
|
||||
double dml_max(double a, double b);
|
||||
@ -38,8 +40,8 @@ bool dml_util_is_420(enum source_format_class sorce_format);
|
||||
double dml_ceil_ex(double x, double granularity);
|
||||
double dml_floor_ex(double x, double granularity);
|
||||
double dml_log(double x, double base);
|
||||
double dml_ceil(double a);
|
||||
double dml_floor(double a);
|
||||
double dml_ceil(double a, double granularity);
|
||||
double dml_floor(double a, double granularity);
|
||||
double dml_round(double a);
|
||||
int dml_log2(double x);
|
||||
double dml_pow(double a, int exp);
|
||||
|
||||
@ -24,49 +24,45 @@
|
||||
*/
|
||||
#include "soc_bounding_box.h"
|
||||
#include "display_mode_lib.h"
|
||||
#include "dc_features.h"
|
||||
|
||||
void dml_socbb_set_latencies(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_soc_bounding_box_st *from_box)
|
||||
void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box)
|
||||
{
|
||||
struct _vcs_dpi_soc_bounding_box_st *to_box = &mode_lib->soc;
|
||||
|
||||
to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
|
||||
to_box->sr_exit_time_us = from_box->sr_exit_time_us;
|
||||
to_box->sr_enter_plus_exit_time_us = from_box->sr_enter_plus_exit_time_us;
|
||||
to_box->urgent_latency_us = from_box->urgent_latency_us;
|
||||
to_box->writeback_latency_us = from_box->writeback_latency_us;
|
||||
DTRACE("box.dram_clock_change_latency_us: %f", from_box->dram_clock_change_latency_us);
|
||||
DTRACE("box.sr_exit_time_us: %f", from_box->sr_exit_time_us);
|
||||
DTRACE("box.sr_enter_plus_exit_time_us: %f", from_box->sr_enter_plus_exit_time_us);
|
||||
DTRACE("box.urgent_latency_us: %f", from_box->urgent_latency_us);
|
||||
DTRACE("box.writeback_latency_us: %f", from_box->writeback_latency_us);
|
||||
|
||||
}
|
||||
|
||||
struct _vcs_dpi_voltage_scaling_st dml_socbb_voltage_scaling(
|
||||
struct _vcs_dpi_soc_bounding_box_st *box,
|
||||
voltage_scaling_st dml_socbb_voltage_scaling(
|
||||
const soc_bounding_box_st *soc,
|
||||
enum voltage_state voltage)
|
||||
{
|
||||
switch (voltage) {
|
||||
case dm_vmin:
|
||||
return box->vmin;
|
||||
case dm_vnom:
|
||||
return box->vnom;
|
||||
case dm_vmax:
|
||||
default:
|
||||
return box->vmax;
|
||||
}
|
||||
const voltage_scaling_st *voltage_state;
|
||||
const voltage_scaling_st * const voltage_end = soc->clock_limits + DC__VOLTAGE_STATES;
|
||||
|
||||
for (voltage_state = soc->clock_limits;
|
||||
voltage_state < voltage_end && voltage_state->state != voltage;
|
||||
voltage_state++) {
|
||||
}
|
||||
|
||||
double dml_socbb_return_bw_mhz(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage)
|
||||
if (voltage_state < voltage_end)
|
||||
return *voltage_state;
|
||||
return soc->clock_limits[DC__VOLTAGE_STATES - 1];
|
||||
}
|
||||
|
||||
double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage)
|
||||
{
|
||||
double return_bw;
|
||||
|
||||
struct _vcs_dpi_voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
|
||||
voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
|
||||
|
||||
return_bw = dml_min((double) box->return_bus_width_bytes * state.dcfclk_mhz,
|
||||
state.dram_bw_per_chan_gbps * 1000.0 * (double) box->num_chans
|
||||
* box->ideal_dram_bw_after_urgent_percent / 100.0);
|
||||
|
||||
return_bw = dml_min((double) box->return_bus_width_bytes * state.fabricclk_mhz, return_bw);
|
||||
|
||||
return_bw = dml_min(
|
||||
((double) box->return_bus_width_bytes) * state.dcfclk_mhz,
|
||||
state.dram_bw_per_chan_gbps * 1000.0 * box->ideal_dram_bw_after_urgent_percent / 100.0);
|
||||
return return_bw;
|
||||
}
|
||||
|
||||
@ -22,15 +22,14 @@
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SOC_BOUNDING_BOX_H__
|
||||
#define __SOC_BOUNDING_BOX_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
void dml_socbb_set_latencies(struct display_mode_lib *mode_lib, struct _vcs_dpi_soc_bounding_box_st *from_box);
|
||||
struct _vcs_dpi_voltage_scaling_st dml_socbb_voltage_scaling(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage);
|
||||
double dml_socbb_return_bw_mhz(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage);
|
||||
void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box);
|
||||
voltage_scaling_st dml_socbb_voltage_scaling(const soc_bounding_box_st *box, enum voltage_state voltage);
|
||||
double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user