mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 05:56:56 +07:00
drm/nouveau/mmu/nv44: implement new vmm backend
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
473f9aca6c
commit
6ce513529a
@ -24,150 +24,16 @@
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#include "vmm.h"
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#include <core/option.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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#define NV44_GART_SIZE (512 * 1024 * 1024)
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#define NV44_GART_PAGE ( 4 * 1024)
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/*******************************************************************************
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* VM map/unmap callbacks
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******************************************************************************/
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static void
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nv44_vm_fill(struct nvkm_memory *pgt, dma_addr_t null,
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dma_addr_t *list, u32 pte, u32 cnt)
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{
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u32 base = (pte << 2) & ~0x0000000f;
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u32 tmp[4];
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tmp[0] = nvkm_ro32(pgt, base + 0x0);
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tmp[1] = nvkm_ro32(pgt, base + 0x4);
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tmp[2] = nvkm_ro32(pgt, base + 0x8);
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tmp[3] = nvkm_ro32(pgt, base + 0xc);
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while (cnt--) {
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u32 addr = list ? (*list++ >> 12) : (null >> 12);
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switch (pte++ & 0x3) {
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case 0:
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tmp[0] &= ~0x07ffffff;
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tmp[0] |= addr;
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break;
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case 1:
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tmp[0] &= ~0xf8000000;
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tmp[0] |= addr << 27;
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tmp[1] &= ~0x003fffff;
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tmp[1] |= addr >> 5;
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break;
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case 2:
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tmp[1] &= ~0xffc00000;
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tmp[1] |= addr << 22;
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tmp[2] &= ~0x0001ffff;
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tmp[2] |= addr >> 10;
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break;
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case 3:
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tmp[2] &= ~0xfffe0000;
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tmp[2] |= addr << 17;
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tmp[3] &= ~0x00000fff;
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tmp[3] |= addr >> 15;
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break;
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}
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}
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nvkm_wo32(pgt, base + 0x0, tmp[0]);
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nvkm_wo32(pgt, base + 0x4, tmp[1]);
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nvkm_wo32(pgt, base + 0x8, tmp[2]);
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nvkm_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
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}
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static void
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nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
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struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
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{
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u32 tmp[4];
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int i;
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nvkm_kmap(pgt);
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if (pte & 3) {
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u32 max = 4 - (pte & 3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_vm_fill(pgt, vma->vm->null, list, pte, part);
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pte += part;
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list += part;
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cnt -= part;
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}
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while (cnt >= 4) {
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for (i = 0; i < 4; i++)
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tmp[i] = *list++ >> 12;
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nvkm_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27);
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nvkm_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22);
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nvkm_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
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nvkm_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
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cnt -= 4;
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}
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if (cnt)
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nv44_vm_fill(pgt, vma->vm->null, list, pte, cnt);
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nvkm_done(pgt);
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}
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static void
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nv44_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
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{
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nvkm_kmap(pgt);
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if (pte & 3) {
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u32 max = 4 - (pte & 3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_vm_fill(pgt, vma->vm->null, NULL, pte, part);
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pte += part;
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cnt -= part;
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}
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while (cnt >= 4) {
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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cnt -= 4;
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}
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if (cnt)
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nv44_vm_fill(pgt, vma->vm->null, NULL, pte, cnt);
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nvkm_done(pgt);
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}
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static void
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nv44_vm_flush(struct nvkm_vm *vm)
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{
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struct nvkm_device *device = vm->mmu->subdev.device;
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nvkm_wr32(device, 0x100814, vm->mmu->limit - NV44_GART_PAGE);
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nvkm_wr32(device, 0x100808, 0x00000020);
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nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x100808) & 0x00000001)
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break;
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);
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nvkm_wr32(device, 0x100808, 0x00000000);
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}
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/*******************************************************************************
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* MMU subdev
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******************************************************************************/
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static int
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nv44_mmu_oneinit(struct nvkm_mmu *mmu)
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{
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mmu->vmm->pgt[0].mem[0] = mmu->vmm->pd->pt[0]->memory;
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mmu->vmm->pgt[0].refcount[0] = 1;
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return 0;
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}
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static void
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nv44_mmu_init(struct nvkm_mmu *mmu)
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{
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struct nvkm_device *device = mmu->subdev.device;
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struct nvkm_memory *gart = mmu->vmm->pgt[0].mem[0];
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struct nvkm_memory *pt = mmu->vmm->pd->pt[0]->memory;
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u32 addr;
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/* calculate vram address of this PRAMIN block, object must be
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@ -175,11 +41,11 @@ nv44_mmu_init(struct nvkm_mmu *mmu)
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* of 512KiB for this to work correctly
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*/
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addr = nvkm_rd32(device, 0x10020c);
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addr -= ((nvkm_memory_addr(gart) >> 19) + 1) << 19;
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addr -= ((nvkm_memory_addr(pt) >> 19) + 1) << 19;
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nvkm_wr32(device, 0x100850, 0x80000000);
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nvkm_wr32(device, 0x100818, mmu->vmm->null);
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nvkm_wr32(device, 0x100804, NV44_GART_SIZE);
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nvkm_wr32(device, 0x100804, (nvkm_memory_size(pt) / 4) * 4096);
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nvkm_wr32(device, 0x100850, 0x00008000);
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nvkm_mask(device, 0x10008c, 0x00000200, 0x00000200);
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nvkm_wr32(device, 0x100820, 0x00000000);
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@ -189,16 +55,12 @@ nv44_mmu_init(struct nvkm_mmu *mmu)
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static const struct nvkm_mmu_func
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nv44_mmu = {
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.oneinit = nv44_mmu_oneinit,
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.init = nv44_mmu_init,
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.limit = NV44_GART_SIZE,
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.dma_bits = 39,
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.pgt_bits = 32 - 12,
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.spg_shift = 12,
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.lpg_shift = 12,
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.map_sg = nv44_vm_map_sg,
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.unmap = nv44_vm_unmap,
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.flush = nv44_vm_flush,
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.vmm = {{ -1, -1, NVIF_CLASS_VMM_NV04}, nv44_vmm_new, true },
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};
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@ -21,8 +21,158 @@
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*/
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#include "vmm.h"
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#include <subdev/timer.h>
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static void
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nv44_vmm_pgt_fill(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
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dma_addr_t *list, u32 ptei, u32 ptes)
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{
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u32 pteo = (ptei << 2) & ~0x0000000f;
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u32 tmp[4];
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tmp[0] = nvkm_ro32(pt->memory, pteo + 0x0);
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tmp[1] = nvkm_ro32(pt->memory, pteo + 0x4);
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tmp[2] = nvkm_ro32(pt->memory, pteo + 0x8);
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tmp[3] = nvkm_ro32(pt->memory, pteo + 0xc);
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while (ptes--) {
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u32 addr = (list ? *list++ : vmm->null) >> 12;
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switch (ptei++ & 0x3) {
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case 0:
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tmp[0] &= ~0x07ffffff;
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tmp[0] |= addr;
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break;
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case 1:
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tmp[0] &= ~0xf8000000;
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tmp[0] |= addr << 27;
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tmp[1] &= ~0x003fffff;
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tmp[1] |= addr >> 5;
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break;
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case 2:
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tmp[1] &= ~0xffc00000;
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tmp[1] |= addr << 22;
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tmp[2] &= ~0x0001ffff;
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tmp[2] |= addr >> 10;
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break;
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case 3:
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tmp[2] &= ~0xfffe0000;
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tmp[2] |= addr << 17;
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tmp[3] &= ~0x00000fff;
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tmp[3] |= addr >> 15;
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break;
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}
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}
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VMM_WO032(pt, vmm, pteo + 0x0, tmp[0]);
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VMM_WO032(pt, vmm, pteo + 0x4, tmp[1]);
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VMM_WO032(pt, vmm, pteo + 0x8, tmp[2]);
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VMM_WO032(pt, vmm, pteo + 0xc, tmp[3] | 0x40000000);
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}
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static void
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nv44_vmm_pgt_pte(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
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u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
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{
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dma_addr_t tmp[4], i;
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if (ptei & 3) {
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const u32 pten = min(ptes, 4 - (ptei & 3));
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for (i = 0; i < pten; i++, addr += 0x1000)
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tmp[i] = addr;
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nv44_vmm_pgt_fill(vmm, pt, tmp, ptei, pten);
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ptei += pten;
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ptes -= pten;
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}
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while (ptes >= 4) {
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for (i = 0; i < 4; i++, addr += 0x1000)
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tmp[i] = addr >> 12;
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[0] >> 0 | tmp[1] << 27);
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[1] >> 5 | tmp[2] << 22);
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[2] >> 10 | tmp[3] << 17);
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[3] >> 15 | 0x40000000);
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ptes -= 4;
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}
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if (ptes) {
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for (i = 0; i < ptes; i++, addr += 0x1000)
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tmp[i] = addr;
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nv44_vmm_pgt_fill(vmm, pt, tmp, ptei, ptes);
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}
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}
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static void
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nv44_vmm_pgt_sgl(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
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u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
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{
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VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, nv44_vmm_pgt_pte);
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}
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static void
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nv44_vmm_pgt_dma(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
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u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
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{
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#if PAGE_SHIFT == 12
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nvkm_kmap(pt->memory);
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if (ptei & 3) {
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const u32 pten = min(ptes, 4 - (ptei & 3));
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nv44_vmm_pgt_fill(vmm, pt, map->dma, ptei, pten);
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ptei += pten;
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ptes -= pten;
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map->dma += pten;
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}
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while (ptes >= 4) {
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u32 tmp[4], i;
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for (i = 0; i < 4; i++)
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tmp[i] = *map->dma++ >> 12;
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[0] >> 0 | tmp[1] << 27);
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[1] >> 5 | tmp[2] << 22);
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[2] >> 10 | tmp[3] << 17);
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VMM_WO032(pt, vmm, ptei++ * 4, tmp[3] >> 15 | 0x40000000);
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ptes -= 4;
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}
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if (ptes) {
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nv44_vmm_pgt_fill(vmm, pt, map->dma, ptei, ptes);
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map->dma += ptes;
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}
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nvkm_done(pt->memory);
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#else
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VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, nv44_vmm_pgt_pte);
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#endif
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}
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static void
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nv44_vmm_pgt_unmap(struct nvkm_vmm *vmm,
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struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
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{
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nvkm_kmap(pt->memory);
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if (ptei & 3) {
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const u32 pten = min(ptes, 4 - (ptei & 3));
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nv44_vmm_pgt_fill(vmm, pt, NULL, ptei, pten);
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ptei += pten;
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ptes -= pten;
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}
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while (ptes > 4) {
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VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
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VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
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VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
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VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
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ptes -= 4;
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}
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if (ptes)
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nv44_vmm_pgt_fill(vmm, pt, NULL, ptei, ptes);
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nvkm_done(pt->memory);
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}
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static const struct nvkm_vmm_desc_func
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nv44_vmm_desc_pgt = {
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.unmap = nv44_vmm_pgt_unmap,
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.dma = nv44_vmm_pgt_dma,
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.sgl = nv44_vmm_pgt_sgl,
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};
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static const struct nvkm_vmm_desc
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@ -31,8 +181,23 @@ nv44_vmm_desc_12[] = {
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{}
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};
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static void
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nv44_vmm_flush(struct nvkm_vmm *vmm, int level)
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{
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struct nvkm_device *device = vmm->mmu->subdev.device;
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nvkm_wr32(device, 0x100814, vmm->limit - 4096);
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nvkm_wr32(device, 0x100808, 0x000000020);
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nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x100808) & 0x00000001)
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break;
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);
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nvkm_wr32(device, 0x100808, 0x00000000);
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}
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static const struct nvkm_vmm_func
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nv44_vmm = {
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.valid = nv04_vmm_valid,
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.flush = nv44_vmm_flush,
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.page = {
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{ 12, &nv44_vmm_desc_12[0], NVKM_VMM_PAGE_HOST },
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{}
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