mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 19:43:54 +07:00
drm/amd/display: rename display clock block to dccg
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
fab55d61b9
commit
6ca1124618
drivers/gpu/drm/amd/display/dc
@ -1948,7 +1948,7 @@ void dc_resource_state_construct(
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const struct dc *dc,
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struct dc_state *dst_ctx)
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{
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dst_ctx->dis_clk = dc->res_pool->display_clock;
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dst_ctx->dis_clk = dc->res_pool->dccg;
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}
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enum dc_status dc_validate_global_state(
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@ -38,7 +38,7 @@
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#include "dal_asic_id.h"
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#define TO_DCE_CLOCKS(clocks)\
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container_of(clocks, struct dce_disp_clk, base)
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container_of(clocks, struct dce_dccg, base)
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#define REG(reg) \
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(clk_dce->regs->reg)
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@ -187,9 +187,9 @@ static int dce_divider_range_get_divider(
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return div;
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}
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static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
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static int dce_clocks_get_dp_ref_freq(struct dccg *clk)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
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int dprefclk_wdivider;
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int dprefclk_src_sel;
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int dp_ref_clk_khz = 600000;
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@ -250,9 +250,9 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
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* or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit
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* clock implementation
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*/
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static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
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static int dce_clocks_get_dp_ref_freq_wrkaround(struct dccg *clk)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
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int dp_ref_clk_khz = 600000;
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if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
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@ -274,10 +274,10 @@ static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
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return dp_ref_clk_khz;
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}
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static enum dm_pp_clocks_state dce_get_required_clocks_state(
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struct display_clock *clk,
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struct dccg *clk,
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struct dc_clocks *req_clocks)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
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int i;
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enum dm_pp_clocks_state low_req_clk;
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@ -306,10 +306,10 @@ static enum dm_pp_clocks_state dce_get_required_clocks_state(
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}
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static int dce_set_clock(
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struct display_clock *clk,
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struct dccg *clk,
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int requested_clk_khz)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
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struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
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struct dc_bios *bp = clk->ctx->dc_bios;
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int actual_clock = requested_clk_khz;
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@ -341,10 +341,10 @@ static int dce_set_clock(
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}
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static int dce_psr_set_clock(
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struct display_clock *clk,
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struct dccg *clk,
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int requested_clk_khz)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
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struct dc_context *ctx = clk_dce->base.ctx;
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struct dc *core_dc = ctx->dc;
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struct dmcu *dmcu = core_dc->res_pool->dmcu;
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@ -357,10 +357,10 @@ static int dce_psr_set_clock(
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}
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static int dce112_set_clock(
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struct display_clock *clk,
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struct dccg *clk,
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int requested_clk_khz)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
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struct bp_set_dce_clock_parameters dce_clk_params;
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struct dc_bios *bp = clk->ctx->dc_bios;
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struct dc *core_dc = clk->ctx->dc;
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@ -409,7 +409,7 @@ static int dce112_set_clock(
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return actual_clock;
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}
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static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
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static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce)
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{
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struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
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struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
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@ -467,7 +467,7 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
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clk_dce->dfs_bypass_enabled = true;
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}
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static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
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static void dce_clock_read_ss_info(struct dce_dccg *clk_dce)
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{
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struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
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int ss_info_num = bp->funcs->get_ss_entry_number(
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@ -523,7 +523,7 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
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}
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}
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static void dce12_update_clocks(struct display_clock *dccg,
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static void dce12_update_clocks(struct dccg *dccg,
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struct dc_clocks *new_clocks,
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bool safe_to_lower)
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{
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@ -549,7 +549,7 @@ static void dce12_update_clocks(struct display_clock *dccg,
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}
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}
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static void dcn_update_clocks(struct display_clock *dccg,
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static void dcn_update_clocks(struct dccg *dccg,
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struct dc_clocks *new_clocks,
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bool safe_to_lower)
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{
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@ -628,7 +628,7 @@ static void dcn_update_clocks(struct display_clock *dccg,
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#endif
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}
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static void dce_update_clocks(struct display_clock *dccg,
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static void dce_update_clocks(struct dccg *dccg,
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struct dc_clocks *new_clocks,
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bool safe_to_lower)
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{
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@ -679,14 +679,14 @@ static const struct display_clock_funcs dce_funcs = {
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.update_clocks = dce_update_clocks
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};
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static void dce_disp_clk_construct(
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struct dce_disp_clk *clk_dce,
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static void dce_dccg_construct(
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struct dce_dccg *clk_dce,
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask)
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{
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struct display_clock *base = &clk_dce->base;
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struct dccg *base = &clk_dce->base;
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base->ctx = ctx;
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base->funcs = &dce_funcs;
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@ -727,13 +727,13 @@ static void dce_disp_clk_construct(
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DIVIDER_RANGE_MAX_DIVIDER_ID);
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}
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struct display_clock *dce_disp_clk_create(
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struct dccg *dce_dccg_create(
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask)
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{
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struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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if (clk_dce == NULL) {
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BREAK_TO_DEBUGGER();
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@ -744,19 +744,19 @@ struct display_clock *dce_disp_clk_create(
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dce80_max_clks_by_state,
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sizeof(dce80_max_clks_by_state));
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dce_disp_clk_construct(
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dce_dccg_construct(
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clk_dce, ctx, regs, clk_shift, clk_mask);
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return &clk_dce->base;
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}
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struct display_clock *dce110_disp_clk_create(
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struct dccg *dce110_dccg_create(
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask)
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{
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struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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if (clk_dce == NULL) {
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BREAK_TO_DEBUGGER();
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@ -767,7 +767,7 @@ struct display_clock *dce110_disp_clk_create(
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dce110_max_clks_by_state,
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sizeof(dce110_max_clks_by_state));
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dce_disp_clk_construct(
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dce_dccg_construct(
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clk_dce, ctx, regs, clk_shift, clk_mask);
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clk_dce->base.funcs = &dce110_funcs;
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@ -775,13 +775,13 @@ struct display_clock *dce110_disp_clk_create(
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return &clk_dce->base;
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}
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struct display_clock *dce112_disp_clk_create(
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struct dccg *dce112_dccg_create(
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask)
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{
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struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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if (clk_dce == NULL) {
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BREAK_TO_DEBUGGER();
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@ -792,7 +792,7 @@ struct display_clock *dce112_disp_clk_create(
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dce112_max_clks_by_state,
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sizeof(dce112_max_clks_by_state));
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dce_disp_clk_construct(
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dce_dccg_construct(
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clk_dce, ctx, regs, clk_shift, clk_mask);
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clk_dce->base.funcs = &dce112_funcs;
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@ -800,9 +800,9 @@ struct display_clock *dce112_disp_clk_create(
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return &clk_dce->base;
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}
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struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
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struct dccg *dce120_dccg_create(struct dc_context *ctx)
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{
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struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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if (clk_dce == NULL) {
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BREAK_TO_DEBUGGER();
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@ -813,7 +813,7 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
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dce120_max_clks_by_state,
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sizeof(dce120_max_clks_by_state));
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dce_disp_clk_construct(
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dce_dccg_construct(
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clk_dce, ctx, NULL, NULL, NULL);
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clk_dce->base.funcs = &dce120_funcs;
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@ -821,9 +821,9 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
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return &clk_dce->base;
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}
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struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)
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struct dccg *dcn_dccg_create(struct dc_context *ctx)
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{
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struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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if (clk_dce == NULL) {
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BREAK_TO_DEBUGGER();
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@ -831,7 +831,7 @@ struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)
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}
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/* TODO strip out useful stuff out of dce constructor */
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dce_disp_clk_construct(
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dce_dccg_construct(
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clk_dce, ctx, NULL, NULL, NULL);
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clk_dce->base.funcs = &dcn_funcs;
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@ -839,10 +839,10 @@ struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)
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return &clk_dce->base;
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}
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void dce_disp_clk_destroy(struct display_clock **disp_clk)
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void dce_dccg_destroy(struct dccg **dccg)
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{
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struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk);
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struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg);
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kfree(clk_dce);
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*disp_clk = NULL;
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*dccg = NULL;
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}
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@ -82,8 +82,8 @@ struct dce_divider_range {
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int did_max;
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};
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struct dce_disp_clk {
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struct display_clock base;
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struct dce_dccg {
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struct dccg base;
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const struct dce_disp_clk_registers *regs;
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const struct dce_disp_clk_shift *clk_shift;
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const struct dce_disp_clk_mask *clk_mask;
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@ -108,28 +108,28 @@ struct dce_disp_clk {
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};
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struct display_clock *dce_disp_clk_create(
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struct dccg *dce_dccg_create(
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask);
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struct display_clock *dce110_disp_clk_create(
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struct dccg *dce110_dccg_create(
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask);
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struct display_clock *dce112_disp_clk_create(
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struct dccg *dce112_dccg_create(
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struct dc_context *ctx,
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const struct dce_disp_clk_registers *regs,
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const struct dce_disp_clk_shift *clk_shift,
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const struct dce_disp_clk_mask *clk_mask);
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struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
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struct dccg *dce120_dccg_create(struct dc_context *ctx);
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struct display_clock *dcn_disp_clk_create(struct dc_context *ctx);
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struct dccg *dcn_dccg_create(struct dc_context *ctx);
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void dce_disp_clk_destroy(struct display_clock **disp_clk);
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void dce_dccg_destroy(struct dccg **dccg);
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#endif /* _DCE_CLOCKS_H_ */
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@ -168,8 +168,8 @@ void dce100_set_bandwidth(
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dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
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dc->res_pool->display_clock->funcs->update_clocks(
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dc->res_pool->display_clock,
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dc->res_pool->dccg->funcs->update_clocks(
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dc->res_pool->dccg,
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&req_clks,
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decrease_allowed);
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@ -644,8 +644,8 @@ static void destruct(struct dce110_resource_pool *pool)
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dce_aud_destroy(&pool->base.audios[i]);
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}
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if (pool->base.display_clock != NULL)
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dce_disp_clk_destroy(&pool->base.display_clock);
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if (pool->base.dccg != NULL)
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dce_dccg_destroy(&pool->base.dccg);
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if (pool->base.abm != NULL)
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dce_abm_destroy(&pool->base.abm);
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@ -817,11 +817,11 @@ static bool construct(
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}
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}
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pool->base.display_clock = dce_disp_clk_create(ctx,
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pool->base.dccg = dce_dccg_create(ctx,
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&disp_clk_regs,
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&disp_clk_shift,
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&disp_clk_mask);
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if (pool->base.display_clock == NULL) {
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if (pool->base.dccg == NULL) {
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dm_error("DC: failed to create display clock!\n");
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BREAK_TO_DEBUGGER();
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goto res_create_fail;
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@ -851,7 +851,7 @@ static bool construct(
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* max_clock_state
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*/
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if (dm_pp_get_static_clocks(ctx, &static_clk_info))
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pool->base.display_clock->max_clks_state =
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pool->base.dccg->max_clks_state =
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static_clk_info.max_clocks_state;
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{
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struct irq_service_init_data init_data;
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@ -2569,8 +2569,8 @@ static void dce110_set_bandwidth(
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else
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dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
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dc->res_pool->display_clock->funcs->update_clocks(
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dc->res_pool->display_clock,
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dc->res_pool->dccg->funcs->update_clocks(
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dc->res_pool->dccg,
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&req_clks,
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decrease_allowed);
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pplib_apply_display_requirements(dc, context);
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@ -679,8 +679,8 @@ static void destruct(struct dce110_resource_pool *pool)
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if (pool->base.dmcu != NULL)
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dce_dmcu_destroy(&pool->base.dmcu);
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||||
|
||||
if (pool->base.display_clock != NULL)
|
||||
dce_disp_clk_destroy(&pool->base.display_clock);
|
||||
if (pool->base.dccg != NULL)
|
||||
dce_dccg_destroy(&pool->base.dccg);
|
||||
|
||||
if (pool->base.irqs != NULL) {
|
||||
dal_irq_service_destroy(&pool->base.irqs);
|
||||
@ -1179,11 +1179,11 @@ static bool construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dce110_disp_clk_create(ctx,
|
||||
pool->base.dccg = dce110_dccg_create(ctx,
|
||||
&disp_clk_regs,
|
||||
&disp_clk_shift,
|
||||
&disp_clk_mask);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto res_create_fail;
|
||||
@ -1213,7 +1213,7 @@ static bool construct(
|
||||
* max_clock_state
|
||||
*/
|
||||
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
|
||||
pool->base.display_clock->max_clks_state =
|
||||
pool->base.dccg->max_clks_state =
|
||||
static_clk_info.max_clocks_state;
|
||||
|
||||
{
|
||||
|
@ -668,8 +668,8 @@ static void destruct(struct dce110_resource_pool *pool)
|
||||
if (pool->base.dmcu != NULL)
|
||||
dce_dmcu_destroy(&pool->base.dmcu);
|
||||
|
||||
if (pool->base.display_clock != NULL)
|
||||
dce_disp_clk_destroy(&pool->base.display_clock);
|
||||
if (pool->base.dccg != NULL)
|
||||
dce_dccg_destroy(&pool->base.dccg);
|
||||
|
||||
if (pool->base.irqs != NULL) {
|
||||
dal_irq_service_destroy(&pool->base.irqs);
|
||||
@ -1124,11 +1124,11 @@ static bool construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dce112_disp_clk_create(ctx,
|
||||
pool->base.dccg = dce112_dccg_create(ctx,
|
||||
&disp_clk_regs,
|
||||
&disp_clk_shift,
|
||||
&disp_clk_mask);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto res_create_fail;
|
||||
@ -1158,7 +1158,7 @@ static bool construct(
|
||||
* max_clock_state
|
||||
*/
|
||||
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
|
||||
pool->base.display_clock->max_clks_state =
|
||||
pool->base.dccg->max_clks_state =
|
||||
static_clk_info.max_clocks_state;
|
||||
|
||||
{
|
||||
|
@ -494,8 +494,8 @@ static void destruct(struct dce110_resource_pool *pool)
|
||||
if (pool->base.dmcu != NULL)
|
||||
dce_dmcu_destroy(&pool->base.dmcu);
|
||||
|
||||
if (pool->base.display_clock != NULL)
|
||||
dce_disp_clk_destroy(&pool->base.display_clock);
|
||||
if (pool->base.dccg != NULL)
|
||||
dce_dccg_destroy(&pool->base.dccg);
|
||||
}
|
||||
|
||||
static void read_dce_straps(
|
||||
@ -894,11 +894,11 @@ static bool construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dce120_disp_clk_create(ctx);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
pool->base.dccg = dce120_dccg_create(ctx);
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto disp_clk_create_fail;
|
||||
goto dccg_create_fail;
|
||||
}
|
||||
|
||||
pool->base.dmcu = dce_dmcu_create(ctx,
|
||||
@ -1011,7 +1011,7 @@ static bool construct(
|
||||
|
||||
irqs_create_fail:
|
||||
controller_create_fail:
|
||||
disp_clk_create_fail:
|
||||
dccg_create_fail:
|
||||
clk_src_create_fail:
|
||||
res_create_fail:
|
||||
|
||||
|
@ -683,8 +683,8 @@ static void destruct(struct dce110_resource_pool *pool)
|
||||
}
|
||||
}
|
||||
|
||||
if (pool->base.display_clock != NULL)
|
||||
dce_disp_clk_destroy(&pool->base.display_clock);
|
||||
if (pool->base.dccg != NULL)
|
||||
dce_dccg_destroy(&pool->base.dccg);
|
||||
|
||||
if (pool->base.irqs != NULL) {
|
||||
dal_irq_service_destroy(&pool->base.irqs);
|
||||
@ -822,11 +822,11 @@ static bool dce80_construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dce_disp_clk_create(ctx,
|
||||
pool->base.dccg = dce_dccg_create(ctx,
|
||||
&disp_clk_regs,
|
||||
&disp_clk_shift,
|
||||
&disp_clk_mask);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto res_create_fail;
|
||||
@ -852,7 +852,7 @@ static bool dce80_construct(
|
||||
goto res_create_fail;
|
||||
}
|
||||
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
|
||||
pool->base.display_clock->max_clks_state =
|
||||
pool->base.dccg->max_clks_state =
|
||||
static_clk_info.max_clocks_state;
|
||||
|
||||
{
|
||||
@ -1006,11 +1006,11 @@ static bool dce81_construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dce_disp_clk_create(ctx,
|
||||
pool->base.dccg = dce_dccg_create(ctx,
|
||||
&disp_clk_regs,
|
||||
&disp_clk_shift,
|
||||
&disp_clk_mask);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto res_create_fail;
|
||||
@ -1037,7 +1037,7 @@ static bool dce81_construct(
|
||||
}
|
||||
|
||||
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
|
||||
pool->base.display_clock->max_clks_state =
|
||||
pool->base.dccg->max_clks_state =
|
||||
static_clk_info.max_clocks_state;
|
||||
|
||||
{
|
||||
@ -1187,11 +1187,11 @@ static bool dce83_construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dce_disp_clk_create(ctx,
|
||||
pool->base.dccg = dce_dccg_create(ctx,
|
||||
&disp_clk_regs,
|
||||
&disp_clk_shift,
|
||||
&disp_clk_mask);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto res_create_fail;
|
||||
@ -1218,7 +1218,7 @@ static bool dce83_construct(
|
||||
}
|
||||
|
||||
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
|
||||
pool->base.display_clock->max_clks_state =
|
||||
pool->base.dccg->max_clks_state =
|
||||
static_clk_info.max_clocks_state;
|
||||
|
||||
{
|
||||
|
@ -2424,8 +2424,8 @@ static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
|
||||
int dispclk_to_dpp_threshold = determine_dppclk_threshold(dc, context);
|
||||
|
||||
/* set disp clk to dpp clk threshold */
|
||||
dc->res_pool->display_clock->funcs->set_dispclk(
|
||||
dc->res_pool->display_clock,
|
||||
dc->res_pool->dccg->funcs->set_dispclk(
|
||||
dc->res_pool->dccg,
|
||||
dispclk_to_dpp_threshold);
|
||||
|
||||
/* update request dpp clk division option */
|
||||
@ -2443,8 +2443,8 @@ static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
|
||||
|
||||
/* If target clk not same as dppclk threshold, set to target clock */
|
||||
if (dispclk_to_dpp_threshold != context->bw.dcn.calc_clk.dispclk_khz) {
|
||||
dc->res_pool->display_clock->funcs->set_dispclk(
|
||||
dc->res_pool->display_clock,
|
||||
dc->res_pool->dccg->funcs->set_dispclk(
|
||||
dc->res_pool->dccg,
|
||||
context->bw.dcn.calc_clk.dispclk_khz);
|
||||
}
|
||||
|
||||
@ -2473,8 +2473,8 @@ static void dcn10_set_bandwidth(
|
||||
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
||||
return;
|
||||
|
||||
dc->res_pool->display_clock->funcs->update_clocks(
|
||||
dc->res_pool->display_clock,
|
||||
dc->res_pool->dccg->funcs->update_clocks(
|
||||
dc->res_pool->dccg,
|
||||
&context->bw.dcn.calc_clk,
|
||||
decrease_allowed);
|
||||
|
||||
|
@ -791,8 +791,8 @@ static void destruct(struct dcn10_resource_pool *pool)
|
||||
if (pool->base.dmcu != NULL)
|
||||
dce_dmcu_destroy(&pool->base.dmcu);
|
||||
|
||||
if (pool->base.display_clock != NULL)
|
||||
dce_disp_clk_destroy(&pool->base.display_clock);
|
||||
if (pool->base.dccg != NULL)
|
||||
dce_dccg_destroy(&pool->base.dccg);
|
||||
|
||||
kfree(pool->base.pp_smu);
|
||||
}
|
||||
@ -1072,8 +1072,8 @@ static bool construct(
|
||||
}
|
||||
}
|
||||
|
||||
pool->base.display_clock = dcn_disp_clk_create(ctx);
|
||||
if (pool->base.display_clock == NULL) {
|
||||
pool->base.dccg = dcn_dccg_create(ctx);
|
||||
if (pool->base.dccg == NULL) {
|
||||
dm_error("DC: failed to create display clock!\n");
|
||||
BREAK_TO_DEBUGGER();
|
||||
goto fail;
|
||||
|
@ -163,7 +163,7 @@ struct resource_pool {
|
||||
unsigned int audio_count;
|
||||
struct audio_support audio_support;
|
||||
|
||||
struct display_clock *display_clock;
|
||||
struct dccg *dccg;
|
||||
struct irq_service *irqs;
|
||||
|
||||
struct abm *abm;
|
||||
@ -282,7 +282,7 @@ struct dc_state {
|
||||
struct dcn_bw_internal_vars dcn_bw_vars;
|
||||
#endif
|
||||
|
||||
struct display_clock *dis_clk;
|
||||
struct dccg *dis_clk;
|
||||
|
||||
struct kref refcount;
|
||||
};
|
||||
|
@ -36,7 +36,7 @@ struct state_dependent_clocks {
|
||||
int pixel_clk_khz;
|
||||
};
|
||||
|
||||
struct display_clock {
|
||||
struct dccg {
|
||||
struct dc_context *ctx;
|
||||
const struct display_clock_funcs *funcs;
|
||||
|
||||
@ -46,13 +46,13 @@ struct display_clock {
|
||||
};
|
||||
|
||||
struct display_clock_funcs {
|
||||
void (*update_clocks)(struct display_clock *dccg,
|
||||
void (*update_clocks)(struct dccg *dccg,
|
||||
struct dc_clocks *new_clocks,
|
||||
bool safe_to_lower);
|
||||
int (*set_dispclk)(struct display_clock *disp_clk,
|
||||
int (*set_dispclk)(struct dccg *dccg,
|
||||
int requested_clock_khz);
|
||||
|
||||
int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
|
||||
int (*get_dp_ref_clk_frequency)(struct dccg *dccg);
|
||||
};
|
||||
|
||||
#endif /* __DISPLAY_CLOCK_H__ */
|
||||
|
Loading…
Reference in New Issue
Block a user