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arm64: tegra: Add L2 cache topology to Tegra210

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Add L2 cache and make it the next level of cache for each of the CPUs.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Joseph Lo 2019-02-01 11:43:47 +08:00 committed by Thierry Reding
parent 3056c1ca29
commit 6c00cac1de
1 changed files with 8 additions and 0 deletions

8
arch/arm64/boot/dts/nvidia/tegra210.dtsi
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@ -1372,6 +1372,7 @@ cpu@0 {
clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
clock-latency = <300000>; clock-latency = <300000>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&L2>;
}; };
cpu@1 { cpu@1 {
@ -1379,6 +1380,7 @@ cpu@1 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <1>; reg = <1>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&L2>;
}; };
cpu@2 { cpu@2 {
@ -1386,6 +1388,7 @@ cpu@2 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <2>; reg = <2>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&L2>;
}; };
cpu@3 { cpu@3 {
@ -1393,6 +1396,7 @@ cpu@3 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <3>; reg = <3>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&L2>;
}; };
idle-states { idle-states {
@ -1409,6 +1413,10 @@ CPU_SLEEP: cpu-sleep {
status = "disabled"; status = "disabled";
}; };
}; };
L2: l2-cache {
compatible = "cache";
};
}; };
timer { timer {