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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
It is mainly a simple merge changing the prefix of some functions to fit the imx-dma namings. As there are no users of the old dma-v1.c api we can safely remove this file. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Javier Martin
Vinod Koul
parent
beeaa103ee
commit
6bd081277e
@ -1,6 +1,3 @@
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config IMX_HAVE_DMA_V1
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bool
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config HAVE_IMX_GPC
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config HAVE_IMX_GPC
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bool
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bool
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@ -26,7 +23,6 @@ config SOC_IMX1
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bool
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bool
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select ARCH_MX1
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select ARCH_MX1
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select CPU_ARM920T
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select CPU_ARM920T
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select IMX_HAVE_DMA_V1
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select IMX_HAVE_IOMUX_V1
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select IMX_HAVE_IOMUX_V1
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select MXC_AVIC
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select MXC_AVIC
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@ -35,7 +31,6 @@ config SOC_IMX21
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select MACH_MX21
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select MACH_MX21
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select CPU_ARM926T
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select CPU_ARM926T
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select ARCH_MXC_AUDMUX_V1
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select ARCH_MXC_AUDMUX_V1
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select IMX_HAVE_DMA_V1
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select IMX_HAVE_IOMUX_V1
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select IMX_HAVE_IOMUX_V1
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select MXC_AVIC
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select MXC_AVIC
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@ -52,7 +47,6 @@ config SOC_IMX27
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select MACH_MX27
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select MACH_MX27
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select CPU_ARM926T
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select CPU_ARM926T
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select ARCH_MXC_AUDMUX_V1
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select ARCH_MXC_AUDMUX_V1
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select IMX_HAVE_DMA_V1
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select IMX_HAVE_IOMUX_V1
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select IMX_HAVE_IOMUX_V1
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select MXC_AVIC
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select MXC_AVIC
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@ -1,5 +1,3 @@
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obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
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obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
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obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
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obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
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obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
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@ -1,846 +0,0 @@
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/*
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* linux/arch/arm/plat-mxc/dma-v1.c
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*
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* i.MX DMA registration and IRQ dispatching
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*
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* Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
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* Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/dma-v1.h>
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#define DMA_DCR 0x00 /* Control Register */
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#define DMA_DISR 0x04 /* Interrupt status Register */
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#define DMA_DIMR 0x08 /* Interrupt mask Register */
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#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
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#define DMA_DRTOSR 0x10 /* Request timeout Register */
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#define DMA_DSESR 0x14 /* Transfer Error Status Register */
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#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
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#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
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#define DMA_WSRA 0x40 /* W-Size Register A */
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#define DMA_XSRA 0x44 /* X-Size Register A */
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#define DMA_YSRA 0x48 /* Y-Size Register A */
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#define DMA_WSRB 0x4c /* W-Size Register B */
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#define DMA_XSRB 0x50 /* X-Size Register B */
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#define DMA_YSRB 0x54 /* Y-Size Register B */
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#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
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#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
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#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
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#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
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#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
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#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
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#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
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#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
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#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
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#define DCR_DRST (1<<1)
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#define DCR_DEN (1<<0)
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#define DBTOCR_EN (1<<15)
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#define DBTOCR_CNT(x) ((x) & 0x7fff)
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#define CNTR_CNT(x) ((x) & 0xffffff)
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#define CCR_ACRPT (1<<14)
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#define CCR_DMOD_LINEAR (0x0 << 12)
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#define CCR_DMOD_2D (0x1 << 12)
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#define CCR_DMOD_FIFO (0x2 << 12)
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#define CCR_DMOD_EOBFIFO (0x3 << 12)
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#define CCR_SMOD_LINEAR (0x0 << 10)
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#define CCR_SMOD_2D (0x1 << 10)
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#define CCR_SMOD_FIFO (0x2 << 10)
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#define CCR_SMOD_EOBFIFO (0x3 << 10)
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#define CCR_MDIR_DEC (1<<9)
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#define CCR_MSEL_B (1<<8)
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#define CCR_DSIZ_32 (0x0 << 6)
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#define CCR_DSIZ_8 (0x1 << 6)
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#define CCR_DSIZ_16 (0x2 << 6)
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#define CCR_SSIZ_32 (0x0 << 4)
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#define CCR_SSIZ_8 (0x1 << 4)
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#define CCR_SSIZ_16 (0x2 << 4)
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#define CCR_REN (1<<3)
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#define CCR_RPT (1<<2)
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#define CCR_FRC (1<<1)
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#define CCR_CEN (1<<0)
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#define RTOR_EN (1<<15)
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#define RTOR_CLK (1<<14)
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#define RTOR_PSC (1<<13)
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/*
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* struct imx_dma_channel - i.MX specific DMA extension
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* @name: name specified by DMA client
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* @irq_handler: client callback for end of transfer
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* @err_handler: client callback for error condition
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* @data: clients context data for callbacks
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* @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
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* @sg: pointer to the actual read/written chunk for scatter-gather emulation
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* @resbytes: total residual number of bytes to transfer
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* (it can be lower or same as sum of SG mapped chunk sizes)
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* @sgcount: number of chunks to be read/written
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*
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* Structure is used for IMX DMA processing. It would be probably good
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* @struct dma_struct in the future for external interfacing and use
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* @struct imx_dma_channel only as extension to it.
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*/
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struct imx_dma_channel {
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const char *name;
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void (*irq_handler) (int, void *);
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void (*err_handler) (int, void *, int errcode);
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void (*prog_handler) (int, void *, struct scatterlist *);
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void *data;
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unsigned int dma_mode;
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struct scatterlist *sg;
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unsigned int resbytes;
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int dma_num;
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int in_use;
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u32 ccr_from_device;
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u32 ccr_to_device;
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struct timer_list watchdog;
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int hw_chaining;
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};
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static void __iomem *imx_dmav1_baseaddr;
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static void imx_dmav1_writel(unsigned val, unsigned offset)
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{
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__raw_writel(val, imx_dmav1_baseaddr + offset);
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}
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static unsigned imx_dmav1_readl(unsigned offset)
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{
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return __raw_readl(imx_dmav1_baseaddr + offset);
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}
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static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
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static struct clk *dma_clk;
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static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
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{
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if (cpu_is_mx27())
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return imxdma->hw_chaining;
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else
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return 0;
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}
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/*
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* imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
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*/
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static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long now;
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__func__, channel);
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return 0;
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}
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now = min(imxdma->resbytes, sg->length);
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if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
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imxdma->resbytes -= now;
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if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
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imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
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else
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imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
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imx_dmav1_writel(now, DMA_CNTR(channel));
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pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
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"size 0x%08x\n", channel,
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imx_dmav1_readl(DMA_DAR(channel)),
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imx_dmav1_readl(DMA_SAR(channel)),
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imx_dmav1_readl(DMA_CNTR(channel)));
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return now;
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}
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/**
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* imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
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* device transfer
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*
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* @channel: i.MX DMA channel number
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* @dma_address: the DMA/physical memory address of the linear data block
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* to transfer
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* @dma_length: length of the data block in bytes
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* @dev_addr: physical device port address
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* Return value: if incorrect parameters are provided -%EINVAL.
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* Zero indicates success.
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*/
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int
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imx_dma_setup_single(int channel, dma_addr_t dma_address,
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unsigned int dma_length, unsigned int dev_addr,
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unsigned int dmamode)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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imxdma->sg = NULL;
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imxdma->dma_mode = dmamode;
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if (!dma_address) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
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channel);
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return -EINVAL;
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}
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if (!dma_length) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
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channel);
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for read\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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imx_dmav1_writel(dev_addr, DMA_SAR(channel));
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imx_dmav1_writel(dma_address, DMA_DAR(channel));
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imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for write\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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imx_dmav1_writel(dma_address, DMA_SAR(channel));
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imx_dmav1_writel(dev_addr, DMA_DAR(channel));
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imx_dmav1_writel(imxdma->ccr_to_device,
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DMA_CCR(channel));
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} else {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
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channel);
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return -EINVAL;
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}
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imx_dmav1_writel(dma_length, DMA_CNTR(channel));
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return 0;
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}
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EXPORT_SYMBOL(imx_dma_setup_single);
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/**
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* imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
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* @channel: i.MX DMA channel number
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* @sg: pointer to the scatter-gather list/vector
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* @sgcount: scatter-gather list hungs count
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* @dma_length: total length of the transfer request in bytes
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* @dev_addr: physical device port address
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* The function sets up DMA channel state and registers to be ready for
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* transfer specified by provided parameters. The scatter-gather emulation
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* is set up according to the parameters.
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*
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* The full preparation of the transfer requires setup of more register
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* by the caller before imx_dma_enable() can be called.
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*
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* %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
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*
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* %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
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*
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* %CCR(channel) has to specify transfer parameters, the next settings is
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* typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
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* specified
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*
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* %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
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*
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* The typical setup for %DMA_MODE_WRITE is specified by next options
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* combination
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*
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* %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
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*
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* Be careful here and do not mistakenly mix source and target device
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* port sizes constants, they are really different:
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* %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
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|
||||||
* %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
|
|
||||||
*
|
|
||||||
* Return value: if incorrect parameters are provided -%EINVAL.
|
|
||||||
* Zero indicates success.
|
|
||||||
*/
|
|
||||||
int
|
|
||||||
imx_dma_setup_sg(int channel,
|
|
||||||
struct scatterlist *sg, unsigned int sgcount,
|
|
||||||
unsigned int dma_length, unsigned int dev_addr,
|
|
||||||
unsigned int dmamode)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
|
|
||||||
if (imxdma->in_use)
|
|
||||||
return -EBUSY;
|
|
||||||
|
|
||||||
imxdma->sg = sg;
|
|
||||||
imxdma->dma_mode = dmamode;
|
|
||||||
imxdma->resbytes = dma_length;
|
|
||||||
|
|
||||||
if (!sg || !sgcount) {
|
|
||||||
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
|
|
||||||
channel);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!sg->length) {
|
|
||||||
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
|
|
||||||
channel);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
|
|
||||||
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
|
|
||||||
"dev_addr=0x%08x for read\n",
|
|
||||||
channel, __func__, sg, sgcount, dma_length, dev_addr);
|
|
||||||
|
|
||||||
imx_dmav1_writel(dev_addr, DMA_SAR(channel));
|
|
||||||
imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
|
|
||||||
} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
|
|
||||||
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
|
|
||||||
"dev_addr=0x%08x for write\n",
|
|
||||||
channel, __func__, sg, sgcount, dma_length, dev_addr);
|
|
||||||
|
|
||||||
imx_dmav1_writel(dev_addr, DMA_DAR(channel));
|
|
||||||
imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
|
|
||||||
} else {
|
|
||||||
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
|
|
||||||
channel);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
imx_dma_sg_next(channel, sg);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_setup_sg);
|
|
||||||
|
|
||||||
int
|
|
||||||
imx_dma_config_channel(int channel, unsigned int config_port,
|
|
||||||
unsigned int config_mem, unsigned int dmareq, int hw_chaining)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
u32 dreq = 0;
|
|
||||||
|
|
||||||
imxdma->hw_chaining = 0;
|
|
||||||
|
|
||||||
if (hw_chaining) {
|
|
||||||
imxdma->hw_chaining = 1;
|
|
||||||
if (!imx_dma_hw_chain(imxdma))
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (dmareq)
|
|
||||||
dreq = CCR_REN;
|
|
||||||
|
|
||||||
imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
|
|
||||||
imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
|
|
||||||
|
|
||||||
imx_dmav1_writel(dmareq, DMA_RSSR(channel));
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_config_channel);
|
|
||||||
|
|
||||||
void imx_dma_config_burstlen(int channel, unsigned int burstlen)
|
|
||||||
{
|
|
||||||
imx_dmav1_writel(burstlen, DMA_BLR(channel));
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_config_burstlen);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
|
|
||||||
* handlers
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
* @irq_handler: the pointer to the function called if the transfer
|
|
||||||
* ends successfully
|
|
||||||
* @err_handler: the pointer to the function called if the premature
|
|
||||||
* end caused by error occurs
|
|
||||||
* @data: user specified value to be passed to the handlers
|
|
||||||
*/
|
|
||||||
int
|
|
||||||
imx_dma_setup_handlers(int channel,
|
|
||||||
void (*irq_handler) (int, void *),
|
|
||||||
void (*err_handler) (int, void *, int),
|
|
||||||
void *data)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!imxdma->name) {
|
|
||||||
printk(KERN_CRIT "%s: called for not allocated channel %d\n",
|
|
||||||
__func__, channel);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
imx_dmav1_writel(1 << channel, DMA_DISR);
|
|
||||||
imxdma->irq_handler = irq_handler;
|
|
||||||
imxdma->err_handler = err_handler;
|
|
||||||
imxdma->data = data;
|
|
||||||
local_irq_restore(flags);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_setup_handlers);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_setup_progression_handler - setup i.MX DMA channel progression
|
|
||||||
* handlers
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
* @prog_handler: the pointer to the function called if the transfer progresses
|
|
||||||
*/
|
|
||||||
int
|
|
||||||
imx_dma_setup_progression_handler(int channel,
|
|
||||||
void (*prog_handler) (int, void*, struct scatterlist*))
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!imxdma->name) {
|
|
||||||
printk(KERN_CRIT "%s: called for not allocated channel %d\n",
|
|
||||||
__func__, channel);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
imxdma->prog_handler = prog_handler;
|
|
||||||
local_irq_restore(flags);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_setup_progression_handler);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_enable - function to start i.MX DMA channel operation
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
*
|
|
||||||
* The channel has to be allocated by driver through imx_dma_request()
|
|
||||||
* or imx_dma_request_by_prio() function.
|
|
||||||
* The transfer parameters has to be set to the channel registers through
|
|
||||||
* call of the imx_dma_setup_single() or imx_dma_setup_sg() function
|
|
||||||
* and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
|
|
||||||
* be set prior this function call by the channel user.
|
|
||||||
*/
|
|
||||||
void imx_dma_enable(int channel)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
pr_debug("imxdma%d: imx_dma_enable\n", channel);
|
|
||||||
|
|
||||||
if (!imxdma->name) {
|
|
||||||
printk(KERN_CRIT "%s: called for not allocated channel %d\n",
|
|
||||||
__func__, channel);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (imxdma->in_use)
|
|
||||||
return;
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
|
|
||||||
imx_dmav1_writel(1 << channel, DMA_DISR);
|
|
||||||
imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
|
|
||||||
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
|
|
||||||
CCR_ACRPT, DMA_CCR(channel));
|
|
||||||
|
|
||||||
if ((cpu_is_mx21() || cpu_is_mx27()) &&
|
|
||||||
imxdma->sg && imx_dma_hw_chain(imxdma)) {
|
|
||||||
imxdma->sg = sg_next(imxdma->sg);
|
|
||||||
if (imxdma->sg) {
|
|
||||||
u32 tmp;
|
|
||||||
imx_dma_sg_next(channel, imxdma->sg);
|
|
||||||
tmp = imx_dmav1_readl(DMA_CCR(channel));
|
|
||||||
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
|
|
||||||
DMA_CCR(channel));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
imxdma->in_use = 1;
|
|
||||||
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_enable);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_disable - stop, finish i.MX DMA channel operatin
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
*/
|
|
||||||
void imx_dma_disable(int channel)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
pr_debug("imxdma%d: imx_dma_disable\n", channel);
|
|
||||||
|
|
||||||
if (imx_dma_hw_chain(imxdma))
|
|
||||||
del_timer(&imxdma->watchdog);
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
|
|
||||||
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
|
|
||||||
DMA_CCR(channel));
|
|
||||||
imx_dmav1_writel(1 << channel, DMA_DISR);
|
|
||||||
imxdma->in_use = 0;
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_disable);
|
|
||||||
|
|
||||||
static void imx_dma_watchdog(unsigned long chno)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
|
|
||||||
|
|
||||||
imx_dmav1_writel(0, DMA_CCR(chno));
|
|
||||||
imxdma->in_use = 0;
|
|
||||||
imxdma->sg = NULL;
|
|
||||||
|
|
||||||
if (imxdma->err_handler)
|
|
||||||
imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
|
|
||||||
}
|
|
||||||
|
|
||||||
static irqreturn_t dma_err_handler(int irq, void *dev_id)
|
|
||||||
{
|
|
||||||
int i, disr;
|
|
||||||
struct imx_dma_channel *imxdma;
|
|
||||||
unsigned int err_mask;
|
|
||||||
int errcode;
|
|
||||||
|
|
||||||
disr = imx_dmav1_readl(DMA_DISR);
|
|
||||||
|
|
||||||
err_mask = imx_dmav1_readl(DMA_DBTOSR) |
|
|
||||||
imx_dmav1_readl(DMA_DRTOSR) |
|
|
||||||
imx_dmav1_readl(DMA_DSESR) |
|
|
||||||
imx_dmav1_readl(DMA_DBOSR);
|
|
||||||
|
|
||||||
if (!err_mask)
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
|
|
||||||
imx_dmav1_writel(disr & err_mask, DMA_DISR);
|
|
||||||
|
|
||||||
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
||||||
if (!(err_mask & (1 << i)))
|
|
||||||
continue;
|
|
||||||
imxdma = &imx_dma_channels[i];
|
|
||||||
errcode = 0;
|
|
||||||
|
|
||||||
if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
|
|
||||||
imx_dmav1_writel(1 << i, DMA_DBTOSR);
|
|
||||||
errcode |= IMX_DMA_ERR_BURST;
|
|
||||||
}
|
|
||||||
if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
|
|
||||||
imx_dmav1_writel(1 << i, DMA_DRTOSR);
|
|
||||||
errcode |= IMX_DMA_ERR_REQUEST;
|
|
||||||
}
|
|
||||||
if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
|
|
||||||
imx_dmav1_writel(1 << i, DMA_DSESR);
|
|
||||||
errcode |= IMX_DMA_ERR_TRANSFER;
|
|
||||||
}
|
|
||||||
if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
|
|
||||||
imx_dmav1_writel(1 << i, DMA_DBOSR);
|
|
||||||
errcode |= IMX_DMA_ERR_BUFFER;
|
|
||||||
}
|
|
||||||
if (imxdma->name && imxdma->err_handler) {
|
|
||||||
imxdma->err_handler(i, imxdma->data, errcode);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
imx_dma_channels[i].sg = NULL;
|
|
||||||
|
|
||||||
printk(KERN_WARNING
|
|
||||||
"DMA timeout on channel %d (%s) -%s%s%s%s\n",
|
|
||||||
i, imxdma->name,
|
|
||||||
errcode & IMX_DMA_ERR_BURST ? " burst" : "",
|
|
||||||
errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
|
|
||||||
errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
|
|
||||||
errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
|
|
||||||
}
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void dma_irq_handle_channel(int chno)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
|
|
||||||
|
|
||||||
if (!imxdma->name) {
|
|
||||||
/*
|
|
||||||
* IRQ for an unregistered DMA channel:
|
|
||||||
* let's clear the interrupts and disable it.
|
|
||||||
*/
|
|
||||||
printk(KERN_WARNING
|
|
||||||
"spurious IRQ for DMA channel %d\n", chno);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (imxdma->sg) {
|
|
||||||
u32 tmp;
|
|
||||||
struct scatterlist *current_sg = imxdma->sg;
|
|
||||||
imxdma->sg = sg_next(imxdma->sg);
|
|
||||||
|
|
||||||
if (imxdma->sg) {
|
|
||||||
imx_dma_sg_next(chno, imxdma->sg);
|
|
||||||
|
|
||||||
tmp = imx_dmav1_readl(DMA_CCR(chno));
|
|
||||||
|
|
||||||
if (imx_dma_hw_chain(imxdma)) {
|
|
||||||
/* FIXME: The timeout should probably be
|
|
||||||
* configurable
|
|
||||||
*/
|
|
||||||
mod_timer(&imxdma->watchdog,
|
|
||||||
jiffies + msecs_to_jiffies(500));
|
|
||||||
|
|
||||||
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
|
|
||||||
imx_dmav1_writel(tmp, DMA_CCR(chno));
|
|
||||||
} else {
|
|
||||||
imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
|
|
||||||
tmp |= CCR_CEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
imx_dmav1_writel(tmp, DMA_CCR(chno));
|
|
||||||
|
|
||||||
if (imxdma->prog_handler)
|
|
||||||
imxdma->prog_handler(chno, imxdma->data,
|
|
||||||
current_sg);
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (imx_dma_hw_chain(imxdma)) {
|
|
||||||
del_timer(&imxdma->watchdog);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
imx_dmav1_writel(0, DMA_CCR(chno));
|
|
||||||
imxdma->in_use = 0;
|
|
||||||
if (imxdma->irq_handler)
|
|
||||||
imxdma->irq_handler(chno, imxdma->data);
|
|
||||||
}
|
|
||||||
|
|
||||||
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
|
||||||
{
|
|
||||||
int i, disr;
|
|
||||||
|
|
||||||
if (cpu_is_mx21() || cpu_is_mx27())
|
|
||||||
dma_err_handler(irq, dev_id);
|
|
||||||
|
|
||||||
disr = imx_dmav1_readl(DMA_DISR);
|
|
||||||
|
|
||||||
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
|
|
||||||
disr);
|
|
||||||
|
|
||||||
imx_dmav1_writel(disr, DMA_DISR);
|
|
||||||
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
||||||
if (disr & (1 << i))
|
|
||||||
dma_irq_handle_channel(i);
|
|
||||||
}
|
|
||||||
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_request - request/allocate specified channel number
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
* @name: the driver/caller own non-%NULL identification
|
|
||||||
*/
|
|
||||||
int imx_dma_request(int channel, const char *name)
|
|
||||||
{
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
unsigned long flags;
|
|
||||||
int ret = 0;
|
|
||||||
|
|
||||||
/* basic sanity checks */
|
|
||||||
if (!name)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
if (channel >= IMX_DMA_CHANNELS) {
|
|
||||||
printk(KERN_CRIT "%s: called for non-existed channel %d\n",
|
|
||||||
__func__, channel);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
if (imxdma->name) {
|
|
||||||
local_irq_restore(flags);
|
|
||||||
return -EBUSY;
|
|
||||||
}
|
|
||||||
memset(imxdma, 0, sizeof(*imxdma));
|
|
||||||
imxdma->name = name;
|
|
||||||
local_irq_restore(flags); /* request_irq() can block */
|
|
||||||
|
|
||||||
if (cpu_is_mx21() || cpu_is_mx27()) {
|
|
||||||
ret = request_irq(MX2x_INT_DMACH0 + channel,
|
|
||||||
dma_irq_handler, 0, "DMA", NULL);
|
|
||||||
if (ret) {
|
|
||||||
imxdma->name = NULL;
|
|
||||||
pr_crit("Can't register IRQ %d for DMA channel %d\n",
|
|
||||||
MX2x_INT_DMACH0 + channel, channel);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
init_timer(&imxdma->watchdog);
|
|
||||||
imxdma->watchdog.function = &imx_dma_watchdog;
|
|
||||||
imxdma->watchdog.data = channel;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_request);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_free - release previously acquired channel
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
*/
|
|
||||||
void imx_dma_free(int channel)
|
|
||||||
{
|
|
||||||
unsigned long flags;
|
|
||||||
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
|
|
||||||
|
|
||||||
if (!imxdma->name) {
|
|
||||||
printk(KERN_CRIT
|
|
||||||
"%s: trying to free free channel %d\n",
|
|
||||||
__func__, channel);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
/* Disable interrupts */
|
|
||||||
imx_dma_disable(channel);
|
|
||||||
imxdma->name = NULL;
|
|
||||||
|
|
||||||
if (cpu_is_mx21() || cpu_is_mx27())
|
|
||||||
free_irq(MX2x_INT_DMACH0 + channel, NULL);
|
|
||||||
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_free);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* imx_dma_request_by_prio - find and request some of free channels best
|
|
||||||
* suiting requested priority
|
|
||||||
* @channel: i.MX DMA channel number
|
|
||||||
* @name: the driver/caller own non-%NULL identification
|
|
||||||
*
|
|
||||||
* This function tries to find a free channel in the specified priority group
|
|
||||||
* if the priority cannot be achieved it tries to look for free channel
|
|
||||||
* in the higher and then even lower priority groups.
|
|
||||||
*
|
|
||||||
* Return value: If there is no free channel to allocate, -%ENODEV is returned.
|
|
||||||
* On successful allocation channel is returned.
|
|
||||||
*/
|
|
||||||
int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
int best;
|
|
||||||
|
|
||||||
switch (prio) {
|
|
||||||
case (DMA_PRIO_HIGH):
|
|
||||||
best = 8;
|
|
||||||
break;
|
|
||||||
case (DMA_PRIO_MEDIUM):
|
|
||||||
best = 4;
|
|
||||||
break;
|
|
||||||
case (DMA_PRIO_LOW):
|
|
||||||
default:
|
|
||||||
best = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = best; i < IMX_DMA_CHANNELS; i++)
|
|
||||||
if (!imx_dma_request(i, name))
|
|
||||||
return i;
|
|
||||||
|
|
||||||
for (i = best - 1; i >= 0; i--)
|
|
||||||
if (!imx_dma_request(i, name))
|
|
||||||
return i;
|
|
||||||
|
|
||||||
printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
|
|
||||||
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(imx_dma_request_by_prio);
|
|
||||||
|
|
||||||
static int __init imx_dma_init(void)
|
|
||||||
{
|
|
||||||
int ret = 0;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (cpu_is_mx1())
|
|
||||||
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
|
|
||||||
else if (cpu_is_mx21())
|
|
||||||
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
|
|
||||||
else if (cpu_is_mx27())
|
|
||||||
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
|
|
||||||
else
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
dma_clk = clk_get(NULL, "dma");
|
|
||||||
if (IS_ERR(dma_clk))
|
|
||||||
return PTR_ERR(dma_clk);
|
|
||||||
clk_enable(dma_clk);
|
|
||||||
|
|
||||||
/* reset DMA module */
|
|
||||||
imx_dmav1_writel(DCR_DRST, DMA_DCR);
|
|
||||||
|
|
||||||
if (cpu_is_mx1()) {
|
|
||||||
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
|
|
||||||
if (ret) {
|
|
||||||
pr_crit("Wow! Can't register IRQ for DMA\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
|
|
||||||
if (ret) {
|
|
||||||
pr_crit("Wow! Can't register ERRIRQ for DMA\n");
|
|
||||||
free_irq(MX1_DMA_INT, NULL);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enable DMA module */
|
|
||||||
imx_dmav1_writel(DCR_DEN, DMA_DCR);
|
|
||||||
|
|
||||||
/* clear all interrupts */
|
|
||||||
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
|
||||||
|
|
||||||
/* disable interrupts */
|
|
||||||
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
|
||||||
|
|
||||||
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
||||||
imx_dma_channels[i].sg = NULL;
|
|
||||||
imx_dma_channels[i].dma_num = i;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
arch_initcall(imx_dma_init);
|
|
||||||
@ -1,103 +0,0 @@
|
|||||||
/*
|
|
||||||
* linux/arch/arm/mach-imx/include/mach/dma-v1.h
|
|
||||||
*
|
|
||||||
* i.MX DMA registration and IRQ dispatching
|
|
||||||
*
|
|
||||||
* Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
||||||
* Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
|
|
||||||
* Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License
|
|
||||||
* as published by the Free Software Foundation; either version 2
|
|
||||||
* of the License, or (at your option) any later version.
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
|
||||||
* MA 02110-1301, USA.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __MACH_DMA_V1_H__
|
|
||||||
#define __MACH_DMA_V1_H__
|
|
||||||
|
|
||||||
#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
|
|
||||||
|
|
||||||
#include <mach/dma.h>
|
|
||||||
|
|
||||||
#define IMX_DMA_CHANNELS 16
|
|
||||||
|
|
||||||
#define DMA_MODE_READ 0
|
|
||||||
#define DMA_MODE_WRITE 1
|
|
||||||
#define DMA_MODE_MASK 1
|
|
||||||
|
|
||||||
#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
|
|
||||||
|
|
||||||
/* DMA Interrupt Mask Register */
|
|
||||||
#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
|
|
||||||
|
|
||||||
/* Channel Control Register */
|
|
||||||
#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
|
|
||||||
|
|
||||||
#define IMX_DMA_MEMSIZE_32 (0 << 4)
|
|
||||||
#define IMX_DMA_MEMSIZE_8 (1 << 4)
|
|
||||||
#define IMX_DMA_MEMSIZE_16 (2 << 4)
|
|
||||||
#define IMX_DMA_TYPE_LINEAR (0 << 10)
|
|
||||||
#define IMX_DMA_TYPE_2D (1 << 10)
|
|
||||||
#define IMX_DMA_TYPE_FIFO (2 << 10)
|
|
||||||
|
|
||||||
#define IMX_DMA_ERR_BURST (1 << 0)
|
|
||||||
#define IMX_DMA_ERR_REQUEST (1 << 1)
|
|
||||||
#define IMX_DMA_ERR_TRANSFER (1 << 2)
|
|
||||||
#define IMX_DMA_ERR_BUFFER (1 << 3)
|
|
||||||
#define IMX_DMA_ERR_TIMEOUT (1 << 4)
|
|
||||||
|
|
||||||
int
|
|
||||||
imx_dma_config_channel(int channel, unsigned int config_port,
|
|
||||||
unsigned int config_mem, unsigned int dmareq, int hw_chaining);
|
|
||||||
|
|
||||||
void
|
|
||||||
imx_dma_config_burstlen(int channel, unsigned int burstlen);
|
|
||||||
|
|
||||||
int
|
|
||||||
imx_dma_setup_single(int channel, dma_addr_t dma_address,
|
|
||||||
unsigned int dma_length, unsigned int dev_addr,
|
|
||||||
unsigned int dmamode);
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use this flag as the dma_length argument to imx_dma_setup_sg()
|
|
||||||
* to create an endless running dma loop. The end of the scatterlist
|
|
||||||
* must be linked to the beginning for this to work.
|
|
||||||
*/
|
|
||||||
#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
|
|
||||||
|
|
||||||
int
|
|
||||||
imx_dma_setup_sg(int channel, struct scatterlist *sg,
|
|
||||||
unsigned int sgcount, unsigned int dma_length,
|
|
||||||
unsigned int dev_addr, unsigned int dmamode);
|
|
||||||
|
|
||||||
int
|
|
||||||
imx_dma_setup_handlers(int channel,
|
|
||||||
void (*irq_handler) (int, void *),
|
|
||||||
void (*err_handler) (int, void *, int), void *data);
|
|
||||||
|
|
||||||
int
|
|
||||||
imx_dma_setup_progression_handler(int channel,
|
|
||||||
void (*prog_handler) (int, void*, struct scatterlist*));
|
|
||||||
|
|
||||||
void imx_dma_enable(int channel);
|
|
||||||
|
|
||||||
void imx_dma_disable(int channel);
|
|
||||||
|
|
||||||
int imx_dma_request(int channel, const char *name);
|
|
||||||
|
|
||||||
void imx_dma_free(int channel);
|
|
||||||
|
|
||||||
int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
|
|
||||||
|
|
||||||
#endif /* __MACH_DMA_V1_H__ */
|
|
||||||
@ -230,7 +230,6 @@ config IMX_SDMA
|
|||||||
|
|
||||||
config IMX_DMA
|
config IMX_DMA
|
||||||
tristate "i.MX DMA support"
|
tristate "i.MX DMA support"
|
||||||
depends on IMX_HAVE_DMA_V1
|
|
||||||
select DMA_ENGINE
|
select DMA_ENGINE
|
||||||
help
|
help
|
||||||
Support the i.MX DMA engine. This engine is integrated into
|
Support the i.MX DMA engine. This engine is integrated into
|
||||||
|
|||||||
@ -14,7 +14,6 @@
|
|||||||
* http://www.opensource.org/licenses/gpl-license.html
|
* http://www.opensource.org/licenses/gpl-license.html
|
||||||
* http://www.gnu.org/copyleft/gpl.html
|
* http://www.gnu.org/copyleft/gpl.html
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
@ -25,15 +24,89 @@
|
|||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
#include <linux/dmaengine.h>
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
|
|
||||||
#include <asm/irq.h>
|
#include <asm/irq.h>
|
||||||
#include <mach/dma-v1.h>
|
#include <mach/dma.h>
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
|
|
||||||
#include "dmaengine.h"
|
#include "dmaengine.h"
|
||||||
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
|
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
|
||||||
|
#define IMX_DMA_CHANNELS 16
|
||||||
|
|
||||||
|
#define DMA_MODE_READ 0
|
||||||
|
#define DMA_MODE_WRITE 1
|
||||||
|
#define DMA_MODE_MASK 1
|
||||||
|
|
||||||
|
#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
|
||||||
|
#define IMX_DMA_MEMSIZE_32 (0 << 4)
|
||||||
|
#define IMX_DMA_MEMSIZE_8 (1 << 4)
|
||||||
|
#define IMX_DMA_MEMSIZE_16 (2 << 4)
|
||||||
|
#define IMX_DMA_TYPE_LINEAR (0 << 10)
|
||||||
|
#define IMX_DMA_TYPE_2D (1 << 10)
|
||||||
|
#define IMX_DMA_TYPE_FIFO (2 << 10)
|
||||||
|
|
||||||
|
#define IMX_DMA_ERR_BURST (1 << 0)
|
||||||
|
#define IMX_DMA_ERR_REQUEST (1 << 1)
|
||||||
|
#define IMX_DMA_ERR_TRANSFER (1 << 2)
|
||||||
|
#define IMX_DMA_ERR_BUFFER (1 << 3)
|
||||||
|
#define IMX_DMA_ERR_TIMEOUT (1 << 4)
|
||||||
|
|
||||||
|
#define DMA_DCR 0x00 /* Control Register */
|
||||||
|
#define DMA_DISR 0x04 /* Interrupt status Register */
|
||||||
|
#define DMA_DIMR 0x08 /* Interrupt mask Register */
|
||||||
|
#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
|
||||||
|
#define DMA_DRTOSR 0x10 /* Request timeout Register */
|
||||||
|
#define DMA_DSESR 0x14 /* Transfer Error Status Register */
|
||||||
|
#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
|
||||||
|
#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
|
||||||
|
#define DMA_WSRA 0x40 /* W-Size Register A */
|
||||||
|
#define DMA_XSRA 0x44 /* X-Size Register A */
|
||||||
|
#define DMA_YSRA 0x48 /* Y-Size Register A */
|
||||||
|
#define DMA_WSRB 0x4c /* W-Size Register B */
|
||||||
|
#define DMA_XSRB 0x50 /* X-Size Register B */
|
||||||
|
#define DMA_YSRB 0x54 /* Y-Size Register B */
|
||||||
|
#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
|
||||||
|
#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
|
||||||
|
#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
|
||||||
|
#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
|
||||||
|
#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
|
||||||
|
#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
|
||||||
|
#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
|
||||||
|
#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
|
||||||
|
#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
|
||||||
|
|
||||||
|
#define DCR_DRST (1<<1)
|
||||||
|
#define DCR_DEN (1<<0)
|
||||||
|
#define DBTOCR_EN (1<<15)
|
||||||
|
#define DBTOCR_CNT(x) ((x) & 0x7fff)
|
||||||
|
#define CNTR_CNT(x) ((x) & 0xffffff)
|
||||||
|
#define CCR_ACRPT (1<<14)
|
||||||
|
#define CCR_DMOD_LINEAR (0x0 << 12)
|
||||||
|
#define CCR_DMOD_2D (0x1 << 12)
|
||||||
|
#define CCR_DMOD_FIFO (0x2 << 12)
|
||||||
|
#define CCR_DMOD_EOBFIFO (0x3 << 12)
|
||||||
|
#define CCR_SMOD_LINEAR (0x0 << 10)
|
||||||
|
#define CCR_SMOD_2D (0x1 << 10)
|
||||||
|
#define CCR_SMOD_FIFO (0x2 << 10)
|
||||||
|
#define CCR_SMOD_EOBFIFO (0x3 << 10)
|
||||||
|
#define CCR_MDIR_DEC (1<<9)
|
||||||
|
#define CCR_MSEL_B (1<<8)
|
||||||
|
#define CCR_DSIZ_32 (0x0 << 6)
|
||||||
|
#define CCR_DSIZ_8 (0x1 << 6)
|
||||||
|
#define CCR_DSIZ_16 (0x2 << 6)
|
||||||
|
#define CCR_SSIZ_32 (0x0 << 4)
|
||||||
|
#define CCR_SSIZ_8 (0x1 << 4)
|
||||||
|
#define CCR_SSIZ_16 (0x2 << 4)
|
||||||
|
#define CCR_REN (1<<3)
|
||||||
|
#define CCR_RPT (1<<2)
|
||||||
|
#define CCR_FRC (1<<1)
|
||||||
|
#define CCR_CEN (1<<0)
|
||||||
|
#define RTOR_EN (1<<15)
|
||||||
|
#define RTOR_CLK (1<<14)
|
||||||
|
#define RTOR_PSC (1<<13)
|
||||||
|
|
||||||
enum imxdma_prep_type {
|
enum imxdma_prep_type {
|
||||||
IMXDMA_DESC_MEMCPY,
|
IMXDMA_DESC_MEMCPY,
|
||||||
@ -42,6 +115,39 @@ enum imxdma_prep_type {
|
|||||||
IMXDMA_DESC_CYCLIC,
|
IMXDMA_DESC_CYCLIC,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* struct imxdma_channel_internal - i.MX specific DMA extension
|
||||||
|
* @name: name specified by DMA client
|
||||||
|
* @irq_handler: client callback for end of transfer
|
||||||
|
* @err_handler: client callback for error condition
|
||||||
|
* @data: clients context data for callbacks
|
||||||
|
* @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
|
||||||
|
* @sg: pointer to the actual read/written chunk for scatter-gather emulation
|
||||||
|
* @resbytes: total residual number of bytes to transfer
|
||||||
|
* (it can be lower or same as sum of SG mapped chunk sizes)
|
||||||
|
* @sgcount: number of chunks to be read/written
|
||||||
|
*
|
||||||
|
* Structure is used for IMX DMA processing. It would be probably good
|
||||||
|
* @struct dma_struct in the future for external interfacing and use
|
||||||
|
* @struct imxdma_channel_internal only as extension to it.
|
||||||
|
*/
|
||||||
|
|
||||||
|
struct imxdma_channel_internal {
|
||||||
|
void *data;
|
||||||
|
unsigned int dma_mode;
|
||||||
|
struct scatterlist *sg;
|
||||||
|
unsigned int resbytes;
|
||||||
|
|
||||||
|
int in_use;
|
||||||
|
|
||||||
|
u32 ccr_from_device;
|
||||||
|
u32 ccr_to_device;
|
||||||
|
|
||||||
|
struct timer_list watchdog;
|
||||||
|
|
||||||
|
int hw_chaining;
|
||||||
|
};
|
||||||
|
|
||||||
struct imxdma_desc {
|
struct imxdma_desc {
|
||||||
struct list_head node;
|
struct list_head node;
|
||||||
struct dma_async_tx_descriptor desc;
|
struct dma_async_tx_descriptor desc;
|
||||||
@ -64,9 +170,9 @@ struct imxdma_desc {
|
|||||||
};
|
};
|
||||||
|
|
||||||
struct imxdma_channel {
|
struct imxdma_channel {
|
||||||
|
struct imxdma_channel_internal internal;
|
||||||
struct imxdma_engine *imxdma;
|
struct imxdma_engine *imxdma;
|
||||||
unsigned int channel;
|
unsigned int channel;
|
||||||
unsigned int imxdma_channel;
|
|
||||||
|
|
||||||
struct tasklet_struct dma_tasklet;
|
struct tasklet_struct dma_tasklet;
|
||||||
struct list_head ld_free;
|
struct list_head ld_free;
|
||||||
@ -84,13 +190,11 @@ struct imxdma_channel {
|
|||||||
struct scatterlist *sg_list;
|
struct scatterlist *sg_list;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define MAX_DMA_CHANNELS 8
|
|
||||||
|
|
||||||
struct imxdma_engine {
|
struct imxdma_engine {
|
||||||
struct device *dev;
|
struct device *dev;
|
||||||
struct device_dma_parameters dma_parms;
|
struct device_dma_parameters dma_parms;
|
||||||
struct dma_device dma_device;
|
struct dma_device dma_device;
|
||||||
struct imxdma_channel channel[MAX_DMA_CHANNELS];
|
struct imxdma_channel channel[IMX_DMA_CHANNELS];
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
|
static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
|
||||||
@ -111,26 +215,379 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void imxdma_irq_handler(int channel, void *data)
|
/* TODO: put this inside any struct */
|
||||||
{
|
static void __iomem *imx_dmav1_baseaddr;
|
||||||
struct imxdma_channel *imxdmac = data;
|
static struct clk *dma_clk;
|
||||||
|
|
||||||
|
static void imx_dmav1_writel(unsigned val, unsigned offset)
|
||||||
|
{
|
||||||
|
__raw_writel(val, imx_dmav1_baseaddr + offset);
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned imx_dmav1_readl(unsigned offset)
|
||||||
|
{
|
||||||
|
return __raw_readl(imx_dmav1_baseaddr + offset);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
|
||||||
|
{
|
||||||
|
if (cpu_is_mx27())
|
||||||
|
return imxdma->hw_chaining;
|
||||||
|
else
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
|
||||||
|
*/
|
||||||
|
static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
|
||||||
|
{
|
||||||
|
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
|
||||||
|
unsigned long now;
|
||||||
|
|
||||||
|
now = min(imxdma->resbytes, sg->length);
|
||||||
|
if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
|
||||||
|
imxdma->resbytes -= now;
|
||||||
|
|
||||||
|
if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
|
||||||
|
imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
|
||||||
|
else
|
||||||
|
imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
|
||||||
|
|
||||||
|
imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
|
||||||
|
|
||||||
|
pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
|
||||||
|
"size 0x%08x\n", imxdmac->channel,
|
||||||
|
imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
|
||||||
|
imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
|
||||||
|
imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
|
||||||
|
|
||||||
|
return now;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
|
||||||
|
unsigned int dma_length, unsigned int dev_addr,
|
||||||
|
unsigned int dmamode)
|
||||||
|
{
|
||||||
|
int channel = imxdmac->channel;
|
||||||
|
|
||||||
|
imxdmac->internal.sg = NULL;
|
||||||
|
imxdmac->internal.dma_mode = dmamode;
|
||||||
|
|
||||||
|
if (!dma_address) {
|
||||||
|
printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
|
||||||
|
channel);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!dma_length) {
|
||||||
|
printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
|
||||||
|
channel);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
|
||||||
|
pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
|
||||||
|
"dev_addr=0x%08x for read\n",
|
||||||
|
channel, __func__, (unsigned int)dma_address,
|
||||||
|
dma_length, dev_addr);
|
||||||
|
|
||||||
|
imx_dmav1_writel(dev_addr, DMA_SAR(channel));
|
||||||
|
imx_dmav1_writel(dma_address, DMA_DAR(channel));
|
||||||
|
imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
|
||||||
|
} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
|
||||||
|
pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
|
||||||
|
"dev_addr=0x%08x for write\n",
|
||||||
|
channel, __func__, (unsigned int)dma_address,
|
||||||
|
dma_length, dev_addr);
|
||||||
|
|
||||||
|
imx_dmav1_writel(dma_address, DMA_SAR(channel));
|
||||||
|
imx_dmav1_writel(dev_addr, DMA_DAR(channel));
|
||||||
|
imx_dmav1_writel(imxdmac->internal.ccr_to_device,
|
||||||
|
DMA_CCR(channel));
|
||||||
|
} else {
|
||||||
|
printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
|
||||||
|
channel);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
imx_dmav1_writel(dma_length, DMA_CNTR(channel));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
|
||||||
|
{
|
||||||
|
int channel = imxdmac->channel;
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
pr_debug("imxdma%d: imx_dma_enable\n", channel);
|
||||||
|
|
||||||
|
if (imxdmac->internal.in_use)
|
||||||
|
return;
|
||||||
|
|
||||||
|
local_irq_save(flags);
|
||||||
|
|
||||||
|
imx_dmav1_writel(1 << channel, DMA_DISR);
|
||||||
|
imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
|
||||||
|
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
|
||||||
|
CCR_ACRPT, DMA_CCR(channel));
|
||||||
|
|
||||||
|
if ((cpu_is_mx21() || cpu_is_mx27()) &&
|
||||||
|
imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
|
||||||
|
imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
|
||||||
|
if (imxdmac->internal.sg) {
|
||||||
|
u32 tmp;
|
||||||
|
imxdma_sg_next(imxdmac, imxdmac->internal.sg);
|
||||||
|
tmp = imx_dmav1_readl(DMA_CCR(channel));
|
||||||
|
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
|
||||||
|
DMA_CCR(channel));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
imxdmac->internal.in_use = 1;
|
||||||
|
|
||||||
|
local_irq_restore(flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
|
||||||
|
{
|
||||||
|
int channel = imxdmac->channel;
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
pr_debug("imxdma%d: imx_dma_disable\n", channel);
|
||||||
|
|
||||||
|
if (imxdma_hw_chain(&imxdmac->internal))
|
||||||
|
del_timer(&imxdmac->internal.watchdog);
|
||||||
|
|
||||||
|
local_irq_save(flags);
|
||||||
|
imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
|
||||||
|
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
|
||||||
|
DMA_CCR(channel));
|
||||||
|
imx_dmav1_writel(1 << channel, DMA_DISR);
|
||||||
|
imxdmac->internal.in_use = 0;
|
||||||
|
local_irq_restore(flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
|
||||||
|
unsigned int config_mem, unsigned int dmareq, int hw_chaining)
|
||||||
|
{
|
||||||
|
int channel = imxdmac->channel;
|
||||||
|
u32 dreq = 0;
|
||||||
|
|
||||||
|
imxdmac->internal.hw_chaining = 0;
|
||||||
|
|
||||||
|
if (hw_chaining) {
|
||||||
|
imxdmac->internal.hw_chaining = 1;
|
||||||
|
if (!imxdma_hw_chain(&imxdmac->internal))
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dmareq)
|
||||||
|
dreq = CCR_REN;
|
||||||
|
|
||||||
|
imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
|
||||||
|
imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
|
||||||
|
|
||||||
|
imx_dmav1_writel(dmareq, DMA_RSSR(channel));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
|
||||||
|
struct scatterlist *sg, unsigned int sgcount,
|
||||||
|
unsigned int dma_length, unsigned int dev_addr,
|
||||||
|
unsigned int dmamode)
|
||||||
|
{
|
||||||
|
int channel = imxdmac->channel;
|
||||||
|
|
||||||
|
if (imxdmac->internal.in_use)
|
||||||
|
return -EBUSY;
|
||||||
|
|
||||||
|
imxdmac->internal.sg = sg;
|
||||||
|
imxdmac->internal.dma_mode = dmamode;
|
||||||
|
imxdmac->internal.resbytes = dma_length;
|
||||||
|
|
||||||
|
if (!sg || !sgcount) {
|
||||||
|
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
|
||||||
|
channel);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!sg->length) {
|
||||||
|
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
|
||||||
|
channel);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
|
||||||
|
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
|
||||||
|
"dev_addr=0x%08x for read\n",
|
||||||
|
channel, __func__, sg, sgcount, dma_length, dev_addr);
|
||||||
|
|
||||||
|
imx_dmav1_writel(dev_addr, DMA_SAR(channel));
|
||||||
|
imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
|
||||||
|
} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
|
||||||
|
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
|
||||||
|
"dev_addr=0x%08x for write\n",
|
||||||
|
channel, __func__, sg, sgcount, dma_length, dev_addr);
|
||||||
|
|
||||||
|
imx_dmav1_writel(dev_addr, DMA_DAR(channel));
|
||||||
|
imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
|
||||||
|
} else {
|
||||||
|
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
|
||||||
|
channel);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
imxdma_sg_next(imxdmac, sg);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void imxdma_watchdog(unsigned long data)
|
||||||
|
{
|
||||||
|
struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
|
||||||
|
int channel = imxdmac->channel;
|
||||||
|
|
||||||
|
imx_dmav1_writel(0, DMA_CCR(channel));
|
||||||
|
imxdmac->internal.in_use = 0;
|
||||||
|
imxdmac->internal.sg = NULL;
|
||||||
|
|
||||||
|
/* Tasklet watchdog error handler */
|
||||||
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
||||||
|
pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
|
||||||
|
}
|
||||||
|
|
||||||
|
static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
struct imxdma_engine *imxdma = dev_id;
|
||||||
|
struct imxdma_channel_internal *internal;
|
||||||
|
unsigned int err_mask;
|
||||||
|
int i, disr;
|
||||||
|
int errcode;
|
||||||
|
|
||||||
|
disr = imx_dmav1_readl(DMA_DISR);
|
||||||
|
|
||||||
|
err_mask = imx_dmav1_readl(DMA_DBTOSR) |
|
||||||
|
imx_dmav1_readl(DMA_DRTOSR) |
|
||||||
|
imx_dmav1_readl(DMA_DSESR) |
|
||||||
|
imx_dmav1_readl(DMA_DBOSR);
|
||||||
|
|
||||||
|
if (!err_mask)
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
|
||||||
|
imx_dmav1_writel(disr & err_mask, DMA_DISR);
|
||||||
|
|
||||||
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
||||||
|
if (!(err_mask & (1 << i)))
|
||||||
|
continue;
|
||||||
|
internal = &imxdma->channel[i].internal;
|
||||||
|
errcode = 0;
|
||||||
|
|
||||||
|
if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
|
||||||
|
imx_dmav1_writel(1 << i, DMA_DBTOSR);
|
||||||
|
errcode |= IMX_DMA_ERR_BURST;
|
||||||
|
}
|
||||||
|
if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
|
||||||
|
imx_dmav1_writel(1 << i, DMA_DRTOSR);
|
||||||
|
errcode |= IMX_DMA_ERR_REQUEST;
|
||||||
|
}
|
||||||
|
if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
|
||||||
|
imx_dmav1_writel(1 << i, DMA_DSESR);
|
||||||
|
errcode |= IMX_DMA_ERR_TRANSFER;
|
||||||
|
}
|
||||||
|
if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
|
||||||
|
imx_dmav1_writel(1 << i, DMA_DBOSR);
|
||||||
|
errcode |= IMX_DMA_ERR_BUFFER;
|
||||||
|
}
|
||||||
|
/* Tasklet error handler */
|
||||||
|
tasklet_schedule(&imxdma->channel[i].dma_tasklet);
|
||||||
|
|
||||||
|
printk(KERN_WARNING
|
||||||
|
"DMA timeout on channel %d -%s%s%s%s\n", i,
|
||||||
|
errcode & IMX_DMA_ERR_BURST ? " burst" : "",
|
||||||
|
errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
|
||||||
|
errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
|
||||||
|
errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
|
||||||
|
}
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
|
||||||
|
{
|
||||||
|
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
|
||||||
|
int chno = imxdmac->channel;
|
||||||
|
|
||||||
|
if (imxdma->sg) {
|
||||||
|
u32 tmp;
|
||||||
|
imxdma->sg = sg_next(imxdma->sg);
|
||||||
|
|
||||||
|
if (imxdma->sg) {
|
||||||
|
imxdma_sg_next(imxdmac, imxdma->sg);
|
||||||
|
|
||||||
|
tmp = imx_dmav1_readl(DMA_CCR(chno));
|
||||||
|
|
||||||
|
if (imxdma_hw_chain(imxdma)) {
|
||||||
|
/* FIXME: The timeout should probably be
|
||||||
|
* configurable
|
||||||
|
*/
|
||||||
|
mod_timer(&imxdma->watchdog,
|
||||||
|
jiffies + msecs_to_jiffies(500));
|
||||||
|
|
||||||
|
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
|
||||||
|
imx_dmav1_writel(tmp, DMA_CCR(chno));
|
||||||
|
} else {
|
||||||
|
imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
|
||||||
|
tmp |= CCR_CEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
imx_dmav1_writel(tmp, DMA_CCR(chno));
|
||||||
|
|
||||||
|
if (imxdma_chan_is_doing_cyclic(imxdmac))
|
||||||
|
/* Tasklet progression */
|
||||||
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (imxdma_hw_chain(imxdma)) {
|
||||||
|
del_timer(&imxdma->watchdog);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
imx_dmav1_writel(0, DMA_CCR(chno));
|
||||||
|
imxdma->in_use = 0;
|
||||||
|
/* Tasklet irq */
|
||||||
tasklet_schedule(&imxdmac->dma_tasklet);
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void imxdma_err_handler(int channel, void *data, int error)
|
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
||||||
{
|
{
|
||||||
struct imxdma_channel *imxdmac = data;
|
struct imxdma_engine *imxdma = dev_id;
|
||||||
|
struct imxdma_channel_internal *internal;
|
||||||
|
int i, disr;
|
||||||
|
|
||||||
tasklet_schedule(&imxdmac->dma_tasklet);
|
if (cpu_is_mx21() || cpu_is_mx27())
|
||||||
}
|
imxdma_err_handler(irq, dev_id);
|
||||||
|
|
||||||
static void imxdma_progression(int channel, void *data,
|
disr = imx_dmav1_readl(DMA_DISR);
|
||||||
struct scatterlist *sg)
|
|
||||||
{
|
|
||||||
struct imxdma_channel *imxdmac = data;
|
|
||||||
|
|
||||||
tasklet_schedule(&imxdmac->dma_tasklet);
|
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
|
||||||
|
disr);
|
||||||
|
|
||||||
|
imx_dmav1_writel(disr, DMA_DISR);
|
||||||
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
||||||
|
if (disr & (1 << i)) {
|
||||||
|
internal = &imxdma->channel[i].internal;
|
||||||
|
dma_irq_handle_channel(&imxdma->channel[i]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int imxdma_xfer_desc(struct imxdma_desc *d)
|
static int imxdma_xfer_desc(struct imxdma_desc *d)
|
||||||
@ -141,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
|
|||||||
/* Configure and enable */
|
/* Configure and enable */
|
||||||
switch (d->type) {
|
switch (d->type) {
|
||||||
case IMXDMA_DESC_MEMCPY:
|
case IMXDMA_DESC_MEMCPY:
|
||||||
ret = imx_dma_config_channel(imxdmac->imxdma_channel,
|
ret = imxdma_config_channel_hw(imxdmac,
|
||||||
d->config_port, d->config_mem, 0, 0);
|
d->config_port, d->config_mem, 0, 0);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
|
ret = imxdma_setup_single_hw(imxdmac, d->src,
|
||||||
d->len, d->dest, d->dmamode);
|
d->len, d->dest, d->dmamode);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
|
||||||
case IMXDMA_DESC_CYCLIC:
|
case IMXDMA_DESC_CYCLIC:
|
||||||
ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
|
|
||||||
imxdma_progression);
|
|
||||||
if (ret < 0)
|
|
||||||
return ret;
|
|
||||||
/*
|
|
||||||
* We fall through here since cyclic transfer is the same as
|
|
||||||
* slave_sg adding a progression handler and a specific sg
|
|
||||||
* configuration which is done in 'imxdma_prep_dma_cyclic'.
|
|
||||||
*/
|
|
||||||
case IMXDMA_DESC_SLAVE_SG:
|
case IMXDMA_DESC_SLAVE_SG:
|
||||||
if (d->dmamode == DMA_MODE_READ)
|
if (d->dmamode == DMA_MODE_READ)
|
||||||
ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
|
ret = imxdma_setup_sg_hw(imxdmac, d->sg,
|
||||||
d->sgcount, d->len, d->src, d->dmamode);
|
d->sgcount, d->len, d->src, d->dmamode);
|
||||||
else
|
else
|
||||||
ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
|
ret = imxdma_setup_sg_hw(imxdmac, d->sg,
|
||||||
d->sgcount, d->len, d->dest, d->dmamode);
|
d->sgcount, d->len, d->dest, d->dmamode);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
@ -173,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
|
|||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
imx_dma_enable(imxdmac->imxdma_channel);
|
imxdma_enable_hw(imxdmac);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -225,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|||||||
|
|
||||||
switch (cmd) {
|
switch (cmd) {
|
||||||
case DMA_TERMINATE_ALL:
|
case DMA_TERMINATE_ALL:
|
||||||
imx_dma_disable(imxdmac->imxdma_channel);
|
imxdma_disable_hw(imxdmac);
|
||||||
|
|
||||||
spin_lock_irqsave(&imxdmac->lock, flags);
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
||||||
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
||||||
@ -255,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|||||||
mode = IMX_DMA_MEMSIZE_32;
|
mode = IMX_DMA_MEMSIZE_32;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
ret = imx_dma_config_channel(imxdmac->imxdma_channel,
|
ret = imxdma_config_channel_hw(imxdmac,
|
||||||
mode | IMX_DMA_TYPE_FIFO,
|
mode | IMX_DMA_TYPE_FIFO,
|
||||||
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
|
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
|
||||||
imxdmac->dma_request, 1);
|
imxdmac->dma_request, 1);
|
||||||
|
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
/* Set burst length */
|
||||||
imx_dma_config_burstlen(imxdmac->imxdma_channel,
|
imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
|
||||||
imxdmac->watermark_level * imxdmac->word_size);
|
DMA_BLR(imxdmac->channel));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
default:
|
default:
|
||||||
@ -333,7 +783,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
|
|||||||
|
|
||||||
spin_lock_irqsave(&imxdmac->lock, flags);
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
||||||
|
|
||||||
imx_dma_disable(imxdmac->imxdma_channel);
|
imxdma_disable_hw(imxdmac);
|
||||||
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
||||||
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
|
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
|
||||||
|
|
||||||
@ -520,10 +970,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static int __init imxdma_probe(struct platform_device *pdev)
|
static int __init imxdma_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct imxdma_engine *imxdma;
|
struct imxdma_engine *imxdma;
|
||||||
int ret, i;
|
int ret, i;
|
||||||
|
|
||||||
|
if (cpu_is_mx1())
|
||||||
|
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
|
||||||
|
else if (cpu_is_mx21())
|
||||||
|
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
|
||||||
|
else if (cpu_is_mx27())
|
||||||
|
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
|
||||||
|
else
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
dma_clk = clk_get(NULL, "dma");
|
||||||
|
if (IS_ERR(dma_clk))
|
||||||
|
return PTR_ERR(dma_clk);
|
||||||
|
clk_enable(dma_clk);
|
||||||
|
|
||||||
|
/* reset DMA module */
|
||||||
|
imx_dmav1_writel(DCR_DRST, DMA_DCR);
|
||||||
|
|
||||||
|
if (cpu_is_mx1()) {
|
||||||
|
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
|
||||||
|
if (ret) {
|
||||||
|
pr_crit("Can't register IRQ for DMA\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
|
||||||
|
if (ret) {
|
||||||
|
pr_crit("Can't register ERRIRQ for DMA\n");
|
||||||
|
free_irq(MX1_DMA_INT, NULL);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* enable DMA module */
|
||||||
|
imx_dmav1_writel(DCR_DEN, DMA_DCR);
|
||||||
|
|
||||||
|
/* clear all interrupts */
|
||||||
|
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
||||||
|
|
||||||
|
/* disable interrupts */
|
||||||
|
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
||||||
|
|
||||||
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
|
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
|
||||||
if (!imxdma)
|
if (!imxdma)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
@ -535,19 +1026,22 @@ static int __init imxdma_probe(struct platform_device *pdev)
|
|||||||
dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
|
dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
|
||||||
|
|
||||||
/* Initialize channel parameters */
|
/* Initialize channel parameters */
|
||||||
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
||||||
struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
||||||
|
memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
|
||||||
imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
|
if (cpu_is_mx21() || cpu_is_mx27()) {
|
||||||
DMA_PRIO_MEDIUM);
|
ret = request_irq(MX2x_INT_DMACH0 + i,
|
||||||
if ((int)imxdmac->channel < 0) {
|
dma_irq_handler, 0, "DMA", imxdma);
|
||||||
ret = -ENODEV;
|
if (ret) {
|
||||||
goto err_init;
|
pr_crit("Can't register IRQ %d for DMA channel %d\n",
|
||||||
|
MX2x_INT_DMACH0 + i, i);
|
||||||
|
goto err_init;
|
||||||
|
}
|
||||||
|
init_timer(&imxdmac->internal.watchdog);
|
||||||
|
imxdmac->internal.watchdog.function = &imxdma_watchdog;
|
||||||
|
imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
|
||||||
}
|
}
|
||||||
|
|
||||||
imx_dma_setup_handlers(imxdmac->imxdma_channel,
|
|
||||||
imxdma_irq_handler, imxdma_err_handler, imxdmac);
|
|
||||||
|
|
||||||
imxdmac->imxdma = imxdma;
|
imxdmac->imxdma = imxdma;
|
||||||
spin_lock_init(&imxdmac->lock);
|
spin_lock_init(&imxdmac->lock);
|
||||||
|
|
||||||
@ -593,9 +1087,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
|
|||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
err_init:
|
err_init:
|
||||||
while (--i >= 0) {
|
|
||||||
struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
if (cpu_is_mx21() || cpu_is_mx27()) {
|
||||||
imx_dma_free(imxdmac->imxdma_channel);
|
while (--i >= 0)
|
||||||
|
free_irq(MX2x_INT_DMACH0 + i, NULL);
|
||||||
|
} else if cpu_is_mx1() {
|
||||||
|
free_irq(MX1_DMA_INT, NULL);
|
||||||
|
free_irq(MX1_DMA_ERR, NULL);
|
||||||
}
|
}
|
||||||
|
|
||||||
kfree(imxdma);
|
kfree(imxdma);
|
||||||
@ -609,10 +1107,12 @@ static int __exit imxdma_remove(struct platform_device *pdev)
|
|||||||
|
|
||||||
dma_async_device_unregister(&imxdma->dma_device);
|
dma_async_device_unregister(&imxdma->dma_device);
|
||||||
|
|
||||||
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
if (cpu_is_mx21() || cpu_is_mx27()) {
|
||||||
struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
for (i = 0; i < IMX_DMA_CHANNELS; i++)
|
||||||
|
free_irq(MX2x_INT_DMACH0 + i, NULL);
|
||||||
imx_dma_free(imxdmac->imxdma_channel);
|
} else if cpu_is_mx1() {
|
||||||
|
free_irq(MX1_DMA_INT, NULL);
|
||||||
|
free_irq(MX1_DMA_ERR, NULL);
|
||||||
}
|
}
|
||||||
|
|
||||||
kfree(imxdma);
|
kfree(imxdma);
|
||||||
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Reference in New Issue
Block a user