mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2.
This is the last part outside of selftests that still don't use the correct lock ordering of timeline->mutex vs resv_lock. With gem fixed, there are a few places that still get locking wrong: - gvt/scheduler.c - i915_perf.c - Most if not all selftests. Changes since v1: - Add intel_engine_pm_get/put() calls to fix use-after-free when using intel_engine_get_pool(). Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200819140904.1708856-16-maarten.lankhorst@linux.intel.com Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Maarten Lankhorst
Joonas Lahtinen
parent
47b086934f
commit
6b05030496
@ -158,6 +158,7 @@ static void clear_pages_worker(struct work_struct *work)
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struct clear_pages_work *w = container_of(work, typeof(*w), work);
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struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
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struct i915_vma *vma = w->sleeve->vma;
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struct i915_gem_ww_ctx ww;
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struct i915_request *rq;
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struct i915_vma *batch;
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int err = w->dma.error;
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@ -173,17 +174,20 @@ static void clear_pages_worker(struct work_struct *work)
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obj->read_domains = I915_GEM_GPU_DOMAINS;
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obj->write_domain = 0;
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (unlikely(err))
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i915_gem_ww_ctx_init(&ww, false);
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intel_engine_pm_get(w->ce->engine);
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retry:
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err = intel_context_pin_ww(w->ce, &ww);
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if (err)
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goto out_signal;
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batch = intel_emit_vma_fill_blt(w->ce, vma, w->value);
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batch = intel_emit_vma_fill_blt(w->ce, vma, &ww, w->value);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_unpin;
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goto out_ctx;
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}
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rq = intel_context_create_request(w->ce);
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rq = i915_request_create(w->ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_batch;
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@ -225,9 +229,19 @@ static void clear_pages_worker(struct work_struct *work)
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i915_request_add(rq);
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out_batch:
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intel_emit_vma_release(w->ce, batch);
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out_unpin:
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i915_vma_unpin(vma);
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out_ctx:
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intel_context_unpin(w->ce);
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out_signal:
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if (err == -EDEADLK) {
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err = i915_gem_ww_ctx_backoff(&ww);
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if (!err)
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goto retry;
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}
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i915_gem_ww_ctx_fini(&ww);
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i915_vma_unpin(w->sleeve->vma);
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intel_engine_pm_put(w->ce->engine);
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if (unlikely(err)) {
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dma_fence_set_error(&w->dma, err);
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dma_fence_signal(&w->dma);
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@ -235,6 +249,44 @@ static void clear_pages_worker(struct work_struct *work)
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}
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}
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static int pin_wait_clear_pages_work(struct clear_pages_work *w,
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struct intel_context *ce)
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{
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struct i915_vma *vma = w->sleeve->vma;
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struct i915_gem_ww_ctx ww;
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int err;
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i915_gem_ww_ctx_init(&ww, false);
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retry:
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err = i915_gem_object_lock(vma->obj, &ww);
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if (err)
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goto out;
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err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
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if (unlikely(err))
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goto out;
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err = i915_sw_fence_await_reservation(&w->wait,
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vma->obj->base.resv, NULL,
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true, 0, I915_FENCE_GFP);
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if (err)
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goto err_unpin_vma;
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dma_resv_add_excl_fence(vma->obj->base.resv, &w->dma);
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err_unpin_vma:
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if (err)
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i915_vma_unpin(vma);
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out:
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if (err == -EDEADLK) {
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err = i915_gem_ww_ctx_backoff(&ww);
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if (!err)
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goto retry;
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}
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i915_gem_ww_ctx_fini(&ww);
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return err;
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}
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static int __i915_sw_fence_call
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clear_pages_work_notify(struct i915_sw_fence *fence,
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enum i915_sw_fence_notify state)
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@ -288,17 +340,9 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj,
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dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0);
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i915_sw_fence_init(&work->wait, clear_pages_work_notify);
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i915_gem_object_lock(obj, NULL);
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err = i915_sw_fence_await_reservation(&work->wait,
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obj->base.resv, NULL, true, 0,
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I915_FENCE_GFP);
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if (err < 0) {
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err = pin_wait_clear_pages_work(work, ce);
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if (err < 0)
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dma_fence_set_error(&work->dma, err);
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} else {
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dma_resv_add_excl_fence(obj->base.resv, &work->dma);
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err = 0;
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}
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i915_gem_object_unlock(obj);
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dma_fence_get(&work->dma);
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i915_sw_fence_commit(&work->wait);
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@ -14,6 +14,7 @@
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struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
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struct i915_vma *vma,
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struct i915_gem_ww_ctx *ww,
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u32 value)
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{
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struct drm_i915_private *i915 = ce->vm->i915;
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@ -39,10 +40,24 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
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goto out_pm;
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}
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err = i915_gem_object_lock(pool->obj, ww);
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if (err)
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goto out_put;
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batch = i915_vma_instance(pool->obj, ce->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_put;
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}
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err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER);
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if (unlikely(err))
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goto out_put;
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cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
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if (IS_ERR(cmd)) {
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err = PTR_ERR(cmd);
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goto out_put;
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goto out_unpin;
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}
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rem = vma->size;
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@ -84,19 +99,11 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
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intel_gt_chipset_flush(ce->vm->gt);
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batch = i915_vma_instance(pool->obj, ce->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_put;
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}
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err = i915_vma_pin(batch, 0, 0, PIN_USER);
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if (unlikely(err))
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goto out_put;
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batch->private = pool;
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return batch;
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out_unpin:
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i915_vma_unpin(batch);
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out_put:
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intel_gt_buffer_pool_put(pool);
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out_pm:
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@ -108,11 +115,9 @@ int intel_emit_vma_mark_active(struct i915_vma *vma, struct i915_request *rq)
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{
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int err;
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i915_vma_lock(vma);
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err = i915_request_await_object(rq, vma->obj, false);
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if (err == 0)
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err = i915_vma_move_to_active(vma, rq, 0);
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i915_vma_unlock(vma);
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if (unlikely(err))
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return err;
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@ -141,6 +146,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
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struct intel_context *ce,
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u32 value)
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{
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struct i915_gem_ww_ctx ww;
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struct i915_request *rq;
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struct i915_vma *batch;
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struct i915_vma *vma;
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@ -150,17 +156,28 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (unlikely(err))
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return err;
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i915_gem_ww_ctx_init(&ww, true);
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intel_engine_pm_get(ce->engine);
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retry:
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err = i915_gem_object_lock(obj, &ww);
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if (err)
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goto out;
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batch = intel_emit_vma_fill_blt(ce, vma, value);
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err = intel_context_pin_ww(ce, &ww);
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if (err)
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goto out;
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err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
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if (err)
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goto out_ctx;
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batch = intel_emit_vma_fill_blt(ce, vma, &ww, value);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_unpin;
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goto out_vma;
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}
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rq = intel_context_create_request(ce);
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rq = i915_request_create(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_batch;
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@ -170,11 +187,9 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
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if (unlikely(err))
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goto out_request;
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i915_vma_lock(vma);
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err = move_obj_to_gpu(vma->obj, rq, true);
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if (err == 0)
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err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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i915_vma_unlock(vma);
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if (unlikely(err))
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goto out_request;
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@ -193,8 +208,18 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
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i915_request_add(rq);
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out_batch:
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intel_emit_vma_release(ce, batch);
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out_unpin:
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out_vma:
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i915_vma_unpin(vma);
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out_ctx:
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intel_context_unpin(ce);
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out:
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if (err == -EDEADLK) {
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err = i915_gem_ww_ctx_backoff(&ww);
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if (!err)
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goto retry;
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}
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i915_gem_ww_ctx_fini(&ww);
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intel_engine_pm_put(ce->engine);
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return err;
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}
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@ -210,6 +235,7 @@ static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size)
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}
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struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
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struct i915_gem_ww_ctx *ww,
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struct i915_vma *src,
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struct i915_vma *dst)
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{
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@ -236,10 +262,24 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
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goto out_pm;
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}
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err = i915_gem_object_lock(pool->obj, ww);
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if (err)
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goto out_put;
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batch = i915_vma_instance(pool->obj, ce->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_put;
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}
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err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER);
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if (unlikely(err))
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goto out_put;
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cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
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if (IS_ERR(cmd)) {
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err = PTR_ERR(cmd);
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goto out_put;
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goto out_unpin;
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}
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rem = src->size;
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@ -296,20 +336,11 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
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i915_gem_object_unpin_map(pool->obj);
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intel_gt_chipset_flush(ce->vm->gt);
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batch = i915_vma_instance(pool->obj, ce->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_put;
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}
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err = i915_vma_pin(batch, 0, 0, PIN_USER);
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if (unlikely(err))
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goto out_put;
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batch->private = pool;
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return batch;
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out_unpin:
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i915_vma_unpin(batch);
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out_put:
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intel_gt_buffer_pool_put(pool);
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out_pm:
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@ -321,10 +352,9 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
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struct drm_i915_gem_object *dst,
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struct intel_context *ce)
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{
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struct drm_gem_object *objs[] = { &src->base, &dst->base };
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struct i915_address_space *vm = ce->vm;
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struct i915_vma *vma[2], *batch;
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struct ww_acquire_ctx acquire;
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struct i915_gem_ww_ctx ww;
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struct i915_request *rq;
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int err, i;
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@ -332,25 +362,36 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
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if (IS_ERR(vma[0]))
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return PTR_ERR(vma[0]);
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err = i915_vma_pin(vma[0], 0, 0, PIN_USER);
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if (unlikely(err))
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return err;
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vma[1] = i915_vma_instance(dst, vm, NULL);
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if (IS_ERR(vma[1]))
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goto out_unpin_src;
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return PTR_ERR(vma);
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err = i915_vma_pin(vma[1], 0, 0, PIN_USER);
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i915_gem_ww_ctx_init(&ww, true);
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intel_engine_pm_get(ce->engine);
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retry:
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err = i915_gem_object_lock(src, &ww);
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if (!err)
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err = i915_gem_object_lock(dst, &ww);
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if (!err)
|
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err = intel_context_pin_ww(ce, &ww);
|
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if (err)
|
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goto out;
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err = i915_vma_pin_ww(vma[0], &ww, 0, 0, PIN_USER);
|
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if (err)
|
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goto out_ctx;
|
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|
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err = i915_vma_pin_ww(vma[1], &ww, 0, 0, PIN_USER);
|
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if (unlikely(err))
|
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goto out_unpin_src;
|
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|
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batch = intel_emit_vma_copy_blt(ce, vma[0], vma[1]);
|
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batch = intel_emit_vma_copy_blt(ce, &ww, vma[0], vma[1]);
|
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if (IS_ERR(batch)) {
|
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err = PTR_ERR(batch);
|
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goto out_unpin_dst;
|
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}
|
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|
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rq = intel_context_create_request(ce);
|
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rq = i915_request_create(ce);
|
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if (IS_ERR(rq)) {
|
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err = PTR_ERR(rq);
|
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goto out_batch;
|
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@ -360,14 +401,10 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
|
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if (unlikely(err))
|
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goto out_request;
|
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|
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err = drm_gem_lock_reservations(objs, ARRAY_SIZE(objs), &acquire);
|
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if (unlikely(err))
|
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goto out_request;
|
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|
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for (i = 0; i < ARRAY_SIZE(vma); i++) {
|
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err = move_obj_to_gpu(vma[i]->obj, rq, i);
|
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if (unlikely(err))
|
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goto out_unlock;
|
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goto out_request;
|
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}
|
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|
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for (i = 0; i < ARRAY_SIZE(vma); i++) {
|
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@ -375,20 +412,19 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
|
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|
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err = i915_vma_move_to_active(vma[i], rq, flags);
|
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if (unlikely(err))
|
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goto out_unlock;
|
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goto out_request;
|
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}
|
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|
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if (rq->engine->emit_init_breadcrumb) {
|
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err = rq->engine->emit_init_breadcrumb(rq);
|
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if (unlikely(err))
|
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goto out_unlock;
|
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goto out_request;
|
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}
|
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|
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err = rq->engine->emit_bb_start(rq,
|
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batch->node.start, batch->node.size,
|
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0);
|
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out_unlock:
|
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drm_gem_unlock_reservations(objs, ARRAY_SIZE(objs), &acquire);
|
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|
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out_request:
|
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if (unlikely(err))
|
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i915_request_set_error_once(rq, err);
|
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@ -400,6 +436,16 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
|
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i915_vma_unpin(vma[1]);
|
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out_unpin_src:
|
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i915_vma_unpin(vma[0]);
|
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out_ctx:
|
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intel_context_unpin(ce);
|
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out:
|
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if (err == -EDEADLK) {
|
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err = i915_gem_ww_ctx_backoff(&ww);
|
||||
if (!err)
|
||||
goto retry;
|
||||
}
|
||||
i915_gem_ww_ctx_fini(&ww);
|
||||
intel_engine_pm_put(ce->engine);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
@ -13,12 +13,15 @@
|
||||
#include "i915_vma.h"
|
||||
|
||||
struct drm_i915_gem_object;
|
||||
struct i915_gem_ww_ctx;
|
||||
|
||||
struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
|
||||
struct i915_vma *vma,
|
||||
struct i915_gem_ww_ctx *ww,
|
||||
u32 value);
|
||||
|
||||
struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
|
||||
struct i915_gem_ww_ctx *ww,
|
||||
struct i915_vma *src,
|
||||
struct i915_vma *dst);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user