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bnx2x: Fix BCM57810-KR AN speed transition
BCM57810-KR link may not come up in 1G after running loopback test, so set the relevant registers to their default values before starting KR autoneg. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -3732,7 +3732,23 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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u16 val16 = 0, lane, bam37 = 0;
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struct bnx2x *bp = params->bp;
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DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
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/* Set to default registers that may be overriden by 10G force */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
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MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_RX66_CONTROL, 0x7415);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
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/* Disable Autoneg: re-enable it after adv is done. */
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
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@ -4402,7 +4418,7 @@ static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
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switch (serdes_net_if) {
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case PORT_HW_CFG_NET_SERDES_IF_KR:
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/* Enable KR Auto Neg */
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if (params->loopback_mode == LOOPBACK_NONE)
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if (params->loopback_mode != LOOPBACK_EXT)
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bnx2x_warpcore_enable_AN_KR(phy, params, vars);
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else {
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DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
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