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[POWERPC] 85xx: Add v1 device tree source for Wind River SBC8560 board
This adds a v1 device tree source for the Wind River SBC8560 board. The biggest difference between this and the MPC8560ADS reference platform dts is the use of an external 16550 compatible UART instead of the CPM2. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Paul Gortmaker
Kumar Gala
parent
2c19806122
commit
6a35b6f09b
330
arch/powerpc/boot/dts/sbc8560.dts
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330
arch/powerpc/boot/dts/sbc8560.dts
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/*
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* SBC8560 Device Tree Source
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*
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* Copyright 2007 Wind River Systems Inc.
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*
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* Paul Gortmaker (see MAINTAINERS for contact information)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "SBC8560";
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compatible = "SBC8560";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8560@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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soc@ff700000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xff700000 0x00100000>;
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reg = <0xff700000 0x00100000>;
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clock-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8560-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 0x2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8560-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <0x20>; // 32 bytes
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <0x10 0x2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@19 {
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interrupt-parent = <&mpic>;
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interrupts = <0x6 0x1>;
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reg = <0x19>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1a {
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interrupt-parent = <&mpic>;
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interrupts = <0x7 0x1>;
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reg = <0x1a>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@1b {
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interrupt-parent = <&mpic>;
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interrupts = <0x8 0x1>;
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reg = <0x1b>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@1c {
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interrupt-parent = <&mpic>;
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interrupts = <0x8 0x1>;
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reg = <0x1c>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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device_type = "open-pic";
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};
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cpm@919c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
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reg = <0x919c0 0x30>;
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ranges;
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muram@80000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000 0x10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0x0 0x4000 0x9000 0x2000>;
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};
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};
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brg@919f0 {
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compatible = "fsl,mpc8560-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <0x919f0 0x10 0x915f0 0x10>;
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clock-frequency = <165000000>;
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};
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cpmpic: pic@90c00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x2e 0x2>;
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interrupt-parent = <&mpic>;
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reg = <0x90c00 0x80>;
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compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
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};
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enet2: ethernet@91320 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x16200300>;
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interrupts = <0x21 0x8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy2>;
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};
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enet3: ethernet@91340 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x1a400300>;
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interrupts = <0x22 0x8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy3>;
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};
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8560-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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pci0: pci@ff708000 {
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cell-index = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xff708000 0x1000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x02 */
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0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
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0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
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0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
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0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <0x18 0x2>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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};
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localbus@ff705000 {
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compatible = "fsl,mpc8560-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xff705000 0x100>; // BRx, ORx, etc.
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ranges = <
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0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
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0x1 0x0 0xe4000000 0x4000000 // 64MB flash
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0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
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0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
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0x5 0x0 0xfc000000 0x0c00000 // EPLD
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0x6 0x0 0xe0000000 0x4000000 // 64MB flash
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0x7 0x0 0x80000000 0x0200000 // ATM1,2
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>;
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epld@5,0 {
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compatible = "wrs,epld-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x5 0x0 0xc00000>;
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ranges = <
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0x0 0x0 0x5 0x000000 0x1fff // LED disp.
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0x1 0x0 0x5 0x100000 0x1fff // switches
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0x2 0x0 0x5 0x200000 0x1fff // ID reg.
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0x3 0x0 0x5 0x300000 0x1fff // status reg.
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0x4 0x0 0x5 0x400000 0x1fff // reset reg.
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0x5 0x0 0x5 0x500000 0x1fff // Wind port
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0x7 0x0 0x5 0x700000 0x1fff // UART #1
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0x8 0x0 0x5 0x800000 0x1fff // UART #2
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0x9 0x0 0x5 0x900000 0x1fff // RTC
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0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
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>;
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bidr@2,0 {
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compatible = "wrs,sbc8560-bidr";
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reg = <0x2 0x0 0x10>;
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};
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bcsr@3,0 {
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compatible = "wrs,sbc8560-bcsr";
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reg = <0x3 0x0 0x10>;
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};
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brstcr@4,0 {
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compatible = "wrs,sbc8560-brstcr";
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reg = <0x4 0x0 0x10>;
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};
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serial0: serial@7,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x7 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <0x9 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@8,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x8 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <0xa 0x2>;
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interrupt-parent = <&mpic>;
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};
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rtc@9,0 {
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compatible = "m48t59";
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reg = <0x9 0x0 0x1fff>;
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};
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};
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};
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};
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