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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 07:47:16 +07:00
drm/amdgpu: batch PDE updates again
Now instead of one submission for each PDE batch them together over all PDs who need an update. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
78eb2f0c71
commit
6989f2460f
@ -1056,118 +1056,46 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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}
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/*
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* amdgpu_vm_update_level - update a single level in the hierarchy
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* amdgpu_vm_update_pde - update a single level in the hierarchy
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*
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* @adev: amdgpu_device pointer
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* @param: parameters for the update
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* @vm: requested vm
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* @parent: parent directory
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* @entry: entry to update
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*
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* Makes sure all entries in @parent are up to date.
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* Returns 0 for success, error for failure.
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* Makes sure the requested entry in parent is up to date.
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*/
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static int amdgpu_vm_update_pde(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_vm_pt *parent,
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struct amdgpu_vm_pt *entry)
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static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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struct amdgpu_vm *vm,
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struct amdgpu_vm_pt *parent,
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struct amdgpu_vm_pt *entry)
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{
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struct amdgpu_pte_update_params params;
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struct amdgpu_bo *bo = entry->base.bo;
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struct amdgpu_bo *shadow;
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struct amdgpu_ring *ring = NULL;
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struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL;
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uint64_t pd_addr, shadow_addr = 0;
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struct amdgpu_job *job;
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struct dma_fence *fence = NULL;
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unsigned ndw = 0;
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uint64_t pde, pt;
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int r;
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if (!parent->entries)
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return 0;
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memset(¶ms, 0, sizeof(params));
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params.adev = adev;
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shadow = parent->base.bo->shadow;
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/* Don't update huge pages here */
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if (entry->huge)
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return;
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if (vm->use_cpu_for_update) {
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pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
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r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
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if (unlikely(r))
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return r;
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params.func = amdgpu_vm_cpu_set_ptes;
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} else {
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ring = container_of(vm->entity.sched, struct amdgpu_ring,
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sched);
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/* should be sufficient for two commands plus padding, etc. */
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ndw = 64;
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pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
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shadow = parent->base.bo->shadow;
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if (shadow)
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shadow_addr = amdgpu_bo_gpu_offset(shadow);
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else
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shadow_addr = 0;
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r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
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if (r)
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return r;
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params.ib = &job->ibs[0];
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params.func = amdgpu_vm_do_set_ptes;
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}
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spin_lock(&vm->status_lock);
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list_del_init(&entry->base.vm_status);
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spin_unlock(&vm->status_lock);
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pt = amdgpu_bo_gpu_offset(bo);
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pt = amdgpu_gart_get_vm_pde(adev, pt);
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/* Don't update huge pages here */
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if (entry->huge) {
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if (!vm->use_cpu_for_update)
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amdgpu_job_free(job);
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return 0;
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}
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pt = amdgpu_gart_get_vm_pde(params->adev, pt);
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if (shadow) {
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pde = shadow_addr + (entry - parent->entries) * 8;
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params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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}
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pde = pd_addr + (entry - parent->entries) * 8;
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params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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if (!vm->use_cpu_for_update) {
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if (params.ib->length_dw == 0) {
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amdgpu_job_free(job);
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} else {
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amdgpu_ring_pad_ib(ring, params.ib);
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amdgpu_sync_resv(adev, &job->sync,
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parent->base.bo->tbo.resv,
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AMDGPU_FENCE_OWNER_VM, false);
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if (shadow)
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amdgpu_sync_resv(adev, &job->sync,
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shadow->tbo.resv,
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AMDGPU_FENCE_OWNER_VM, false);
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WARN_ON(params.ib->length_dw > ndw);
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r = amdgpu_job_submit(job, ring, &vm->entity,
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AMDGPU_FENCE_OWNER_VM, &fence);
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if (r)
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goto error_free;
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amdgpu_bo_fence(parent->base.bo, fence, true);
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dma_fence_put(vm->last_update);
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vm->last_update = fence;
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}
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}
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return 0;
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error_free:
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amdgpu_job_free(job);
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return r;
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params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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}
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/*
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@ -1215,41 +1143,63 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
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int amdgpu_vm_update_directories(struct amdgpu_device *adev,
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struct amdgpu_vm *vm)
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{
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struct amdgpu_pte_update_params params;
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struct amdgpu_job *job;
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unsigned ndw = 0;
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int r = 0;
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if (list_empty(&vm->relocated))
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return 0;
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restart:
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memset(¶ms, 0, sizeof(params));
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params.adev = adev;
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if (vm->use_cpu_for_update) {
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r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
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if (unlikely(r))
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return r;
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params.func = amdgpu_vm_cpu_set_ptes;
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} else {
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ndw = 512 * 8;
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r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
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if (r)
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return r;
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params.ib = &job->ibs[0];
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params.func = amdgpu_vm_do_set_ptes;
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}
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spin_lock(&vm->status_lock);
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while (!list_empty(&vm->relocated)) {
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struct amdgpu_vm_bo_base *bo_base;
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struct amdgpu_vm_bo_base *bo_base, *parent;
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struct amdgpu_vm_pt *pt, *entry;
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struct amdgpu_bo *bo;
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bo_base = list_first_entry(&vm->relocated,
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struct amdgpu_vm_bo_base,
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vm_status);
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list_del_init(&bo_base->vm_status);
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spin_unlock(&vm->status_lock);
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bo = bo_base->bo->parent;
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if (bo) {
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struct amdgpu_vm_bo_base *parent;
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struct amdgpu_vm_pt *pt, *entry;
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parent = list_first_entry(&bo->va,
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struct amdgpu_vm_bo_base,
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bo_list);
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pt = container_of(parent, struct amdgpu_vm_pt, base);
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entry = container_of(bo_base, struct amdgpu_vm_pt,
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base);
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r = amdgpu_vm_update_pde(adev, vm, pt, entry);
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if (r) {
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amdgpu_vm_invalidate_level(adev, vm,
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&vm->root, 0);
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return r;
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}
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if (!bo) {
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spin_lock(&vm->status_lock);
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} else {
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spin_lock(&vm->status_lock);
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list_del_init(&bo_base->vm_status);
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continue;
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}
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parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
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bo_list);
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pt = container_of(parent, struct amdgpu_vm_pt, base);
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entry = container_of(bo_base, struct amdgpu_vm_pt, base);
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amdgpu_vm_update_pde(¶ms, vm, pt, entry);
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spin_lock(&vm->status_lock);
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if (!vm->use_cpu_for_update &&
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(ndw - params.ib->length_dw) < 32)
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break;
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}
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spin_unlock(&vm->status_lock);
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@ -1257,8 +1207,43 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
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/* Flush HDP */
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mb();
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amdgpu_gart_flush_gpu_tlb(adev, 0);
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} else if (params.ib->length_dw == 0) {
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amdgpu_job_free(job);
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} else {
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struct amdgpu_bo *root = vm->root.base.bo;
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struct amdgpu_ring *ring;
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struct dma_fence *fence;
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ring = container_of(vm->entity.sched, struct amdgpu_ring,
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sched);
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amdgpu_ring_pad_ib(ring, params.ib);
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amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
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AMDGPU_FENCE_OWNER_VM, false);
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if (root->shadow)
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amdgpu_sync_resv(adev, &job->sync,
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root->shadow->tbo.resv,
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AMDGPU_FENCE_OWNER_VM, false);
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WARN_ON(params.ib->length_dw > ndw);
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r = amdgpu_job_submit(job, ring, &vm->entity,
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AMDGPU_FENCE_OWNER_VM, &fence);
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if (r)
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goto error;
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amdgpu_bo_fence(root, fence, true);
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dma_fence_put(vm->last_update);
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vm->last_update = fence;
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}
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if (!list_empty(&vm->relocated))
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goto restart;
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return 0;
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error:
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amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0);
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amdgpu_job_free(job);
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return r;
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}
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