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powerpc/powernv/npu: Use the correct IOMMU page size
This uses the page size from iommu_table instead of hard-coded 4K. This should cause no change in behavior. While we are here, move bits around to prepare for further rework which will define and use iommu_table_group_ops. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -204,8 +204,7 @@ static void pnv_npu_disable_bypass(struct pnv_ioda_pe *npe)
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struct pnv_phb *phb = npe->phb;
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struct pci_dev *gpdev;
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struct pnv_ioda_pe *gpe;
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void *addr;
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unsigned int size;
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struct iommu_table *tbl;
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int64_t rc;
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/*
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@ -219,11 +218,11 @@ static void pnv_npu_disable_bypass(struct pnv_ioda_pe *npe)
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if (!gpe)
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return;
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addr = (void *)gpe->table_group.tables[0]->it_base;
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size = gpe->table_group.tables[0]->it_size << 3;
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tbl = gpe->table_group.tables[0];
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rc = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number,
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npe->pe_number, 1, __pa(addr),
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size, 0x1000);
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npe->pe_number, 1, __pa(tbl->it_base),
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tbl->it_size << 3,
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IOMMU_PAGE_SIZE(tbl));
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if (rc != OPAL_SUCCESS)
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pr_warn("%s: Error %lld setting DMA window on PHB#%d-PE#%d\n",
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__func__, rc, phb->hose->global_number, npe->pe_number);
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