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ARM: sun8i: smp: Add support for A83T
Add the support for A83T. A83T SoC has an additional register than A80 to handle CPU configurations: R_CPUS_CFG. Information about the register comes from Allwinner's BSP driver. An important difference is the Power Off Gating register for clusters which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T. There is also a bit swap between sun8i-a83t and sun9i-a80 that must be handled. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Mylène Josserand
Maxime Ripard
parent
1631090e34
commit
6961275e72
@ -51,7 +51,7 @@ config MACH_SUN9I
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config ARCH_SUNXI_MC_SMP
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bool
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depends on SMP
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default MACH_SUN9I
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default MACH_SUN9I || MACH_SUN8I
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select ARM_CCI400_PORT_CTRL
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select ARM_CPU_SUSPEND
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@ -55,22 +55,31 @@
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#define CPUCFG_CX_RST_CTRL_L2_RST BIT(8)
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#define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n))
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#define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
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#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0)
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#define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c))
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#define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n)
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#define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf
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#define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c))
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/* The power off register for clusters are different from a80 and a83t */
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#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0)
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#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4)
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#define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
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#define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu))
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#define PRCM_CPU_SOFT_ENTRY_REG 0x164
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/* R_CPUCFG registers, specific to sun8i-a83t */
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#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4)
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#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n)
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#define R_CPUCFG_CPU_SOFT_ENTRY_REG 0x01a4
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#define CPU0_SUPPORT_HOTPLUG_MAGIC0 0xFA50392F
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#define CPU0_SUPPORT_HOTPLUG_MAGIC1 0x790DCA3A
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static void __iomem *cpucfg_base;
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static void __iomem *prcm_base;
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static void __iomem *sram_b_smp_base;
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static void __iomem *r_cpucfg_base;
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extern void sunxi_mc_smp_secondary_startup(void);
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extern void sunxi_mc_smp_resume(void);
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@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
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reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
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writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
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if (is_a83t) {
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/* assert cpu power-on reset */
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reg = readl(r_cpucfg_base +
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R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
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reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
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writel(reg, r_cpucfg_base +
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R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
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udelay(10);
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}
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/* Cortex-A7: hold L1 reset disable signal low */
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if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
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reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
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@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
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/* open power switch */
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sunxi_cpu_power_switch_set(cpu, cluster, true);
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/* Handle A83T bit swap */
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if (is_a83t) {
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if (cpu == 0)
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cpu = 4;
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}
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/* clear processor power gate */
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reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
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reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
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writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
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udelay(20);
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/* Handle A83T bit swap */
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if (is_a83t) {
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if (cpu == 4)
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cpu = 0;
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}
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/* de-assert processor power-on reset */
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reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
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reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
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writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
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if (is_a83t) {
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reg = readl(r_cpucfg_base +
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R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
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reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
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writel(reg, r_cpucfg_base +
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R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
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udelay(10);
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}
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/* de-assert all processor resets */
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reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
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reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
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@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
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if (cluster >= SUNXI_NR_CLUSTERS)
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return -EINVAL;
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/* For A83T, assert cluster cores resets */
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if (is_a83t) {
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reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
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reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset */
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writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
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udelay(10);
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}
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/* assert ACINACTM */
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reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
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reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
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@ -226,6 +274,16 @@ static int sunxi_cluster_powerup(unsigned int cluster)
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reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
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writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
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/* assert cluster cores resets */
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if (is_a83t) {
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reg = readl(r_cpucfg_base +
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R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
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reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
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writel(reg, r_cpucfg_base +
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R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
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udelay(10);
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}
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/* assert cluster resets */
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reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
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reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
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@ -256,7 +314,10 @@ static int sunxi_cluster_powerup(unsigned int cluster)
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/* clear cluster power gate */
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reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
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reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
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if (is_a83t)
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reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
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else
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reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
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writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
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udelay(20);
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@ -453,7 +514,10 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
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/* gate cluster power */
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pr_debug("%s: gate cluster power\n", __func__);
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reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
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reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
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if (is_a83t)
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reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
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else
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reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
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writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
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udelay(20);
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@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
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return !ret;
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}
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static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
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static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
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{
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/* CPU0 hotplug not handled for sun8i-a83t */
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if (is_a83t)
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if (cpu == 0)
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return false;
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return true;
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}
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#endif
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@ -619,6 +687,7 @@ struct sunxi_mc_smp_nodes {
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struct device_node *prcm_node;
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struct device_node *cpucfg_node;
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struct device_node *sram_node;
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struct device_node *r_cpucfg_node;
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};
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/* This structure holds SoC-specific bits tied to an enable-method string. */
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@ -633,6 +702,7 @@ static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
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of_node_put(nodes->prcm_node);
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of_node_put(nodes->cpucfg_node);
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of_node_put(nodes->sram_node);
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of_node_put(nodes->r_cpucfg_node);
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memset(nodes, 0, sizeof(*nodes));
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}
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@ -662,11 +732,42 @@ static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
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return 0;
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}
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static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
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{
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nodes->prcm_node = of_find_compatible_node(NULL, NULL,
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"allwinner,sun8i-a83t-r-ccu");
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if (!nodes->prcm_node) {
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pr_err("%s: PRCM not available\n", __func__);
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return -ENODEV;
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}
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nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
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"allwinner,sun8i-a83t-cpucfg");
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if (!nodes->cpucfg_node) {
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pr_err("%s: CPUCFG not available\n", __func__);
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return -ENODEV;
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}
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nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
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"allwinner,sun8i-a83t-r-cpucfg");
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if (!nodes->r_cpucfg_node) {
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pr_err("%s: RCPUCFG not available\n", __func__);
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return -ENODEV;
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}
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return 0;
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}
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static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
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{
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.enable_method = "allwinner,sun9i-a80-smp",
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.get_smp_nodes = sun9i_a80_get_smp_nodes,
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},
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{
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.enable_method = "allwinner,sun8i-a83t-smp",
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.get_smp_nodes = sun8i_a83t_get_smp_nodes,
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.is_a83t = true,
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},
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};
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static int __init sunxi_mc_smp_init(void)
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@ -674,6 +775,7 @@ static int __init sunxi_mc_smp_init(void)
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struct sunxi_mc_smp_nodes nodes = { 0 };
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struct device_node *node;
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struct resource res;
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void __iomem *addr;
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int i, ret;
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/*
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@ -738,12 +840,23 @@ static int __init sunxi_mc_smp_init(void)
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goto err_unmap_prcm;
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}
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sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
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"sunxi-mc-smp");
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if (IS_ERR(sram_b_smp_base)) {
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ret = PTR_ERR(sram_b_smp_base);
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pr_err("%s: failed to map secure SRAM\n", __func__);
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goto err_unmap_release_cpucfg;
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if (is_a83t) {
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r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
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0, "sunxi-mc-smp");
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if (IS_ERR(r_cpucfg_base)) {
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ret = PTR_ERR(r_cpucfg_base);
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pr_err("%s: failed to map R-CPUCFG registers\n",
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__func__);
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goto err_unmap_release_cpucfg;
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}
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} else {
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sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
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"sunxi-mc-smp");
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if (IS_ERR(sram_b_smp_base)) {
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ret = PTR_ERR(sram_b_smp_base);
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pr_err("%s: failed to map secure SRAM\n", __func__);
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goto err_unmap_release_cpucfg;
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}
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}
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/* Configure CCI-400 for boot cluster */
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@ -751,15 +864,18 @@ static int __init sunxi_mc_smp_init(void)
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if (ret) {
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pr_err("%s: failed to configure boot cluster: %d\n",
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__func__, ret);
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goto err_unmap_release_secure_sram;
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goto err_unmap_release_sram_rcpucfg;
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}
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/* We don't need the device nodes anymore */
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sunxi_mc_smp_put_nodes(&nodes);
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/* Set the hardware entry point address */
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writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
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prcm_base + PRCM_CPU_SOFT_ENTRY_REG);
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if (is_a83t)
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addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
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else
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addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
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writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
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/* Actually enable multi cluster SMP */
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smp_set_ops(&sunxi_mc_smp_smp_ops);
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@ -768,9 +884,14 @@ static int __init sunxi_mc_smp_init(void)
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return 0;
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err_unmap_release_secure_sram:
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iounmap(sram_b_smp_base);
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of_address_to_resource(nodes.sram_node, 0, &res);
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err_unmap_release_sram_rcpucfg:
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if (is_a83t) {
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iounmap(r_cpucfg_base);
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of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
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} else {
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iounmap(sram_b_smp_base);
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of_address_to_resource(nodes.sram_node, 0, &res);
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}
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release_mem_region(res.start, resource_size(&res));
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err_unmap_release_cpucfg:
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iounmap(cpucfg_base);
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