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be2net: Use new F/W mailbox cmd to manipulate interrupts.
This is needed as the earlier method of manipulating this register via PCI Config space is disallowed by certain Hypervisors. Signed-off-by: Somnath Kotur <somnath.kotur@emulex.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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8cef7a7892
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@ -3202,6 +3202,31 @@ int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
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return status;
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}
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int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
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{
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struct be_mcc_wrb *wrb;
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struct be_cmd_req_intr_set *req;
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int status;
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if (mutex_lock_interruptible(&adapter->mbox_lock))
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return -1;
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wrb = wrb_from_mbox(adapter);
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req = embedded_payload(wrb);
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be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
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wrb, NULL);
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req->intr_enabled = intr_enable;
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status = be_mbox_notify_wait(adapter);
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mutex_unlock(&adapter->mbox_lock);
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return status;
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}
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int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
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int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
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{
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@ -188,6 +188,7 @@ struct be_mcc_mailbox {
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#define OPCODE_COMMON_GET_BEACON_STATE 70
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#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
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#define OPCODE_COMMON_GET_PORT_NAME 77
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#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
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#define OPCODE_COMMON_GET_PHY_DETAILS 102
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#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
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#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
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@ -1791,6 +1792,12 @@ struct be_cmd_enable_disable_vf {
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u8 rsvd[3];
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};
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struct be_cmd_req_intr_set {
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struct be_cmd_req_hdr hdr;
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u8 intr_enabled;
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u8 rsvd[3];
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};
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static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
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{
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return flags & adapter->cmd_privileges ? true : false;
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@ -1938,3 +1945,4 @@ extern int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
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extern int be_cmd_get_if_id(struct be_adapter *adapter,
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struct be_vf_cfg *vf_cfg, int vf_num);
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extern int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
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extern int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
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@ -153,17 +153,10 @@ static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
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return 0;
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}
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static void be_intr_set(struct be_adapter *adapter, bool enable)
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static void be_reg_intr_set(struct be_adapter *adapter, bool enable)
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{
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u32 reg, enabled;
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/* On lancer interrupts can't be controlled via this register */
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if (lancer_chip(adapter))
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return;
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if (adapter->eeh_error)
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return;
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pci_read_config_dword(adapter->pdev, PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET,
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®);
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enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
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@ -179,6 +172,22 @@ static void be_intr_set(struct be_adapter *adapter, bool enable)
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PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, reg);
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}
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static void be_intr_set(struct be_adapter *adapter, bool enable)
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{
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int status = 0;
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/* On lancer interrupts can't be controlled via this register */
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if (lancer_chip(adapter))
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return;
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if (adapter->eeh_error)
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return;
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status = be_cmd_intr_set(adapter, enable);
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if (status)
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be_reg_intr_set(adapter, enable);
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}
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static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
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{
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u32 val = 0;
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