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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 05:30:54 +07:00
[TG3]: Add indirect register method for 5703 behind ICH
This patch adds the new workaround for 5703 A1/A2 if it is behind certain ICH bridges. The workaround disables memory and uses config. cycles only to access all registers. The 5702/03 chips can mistakenly decode the special cycles from the ICH chipsets as memory write cycles, causing corruption of register and memory space. Only certain ICH bridges will drive special cycles with non-zero data during the address phase which can fall within the 5703's address range. This is not an ICH bug as the PCI spec allows non-zero address during special cycles. However, only these ICH bridges are known to drive non-zero addresses during special cycles. The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh because it is used in irq handler when using the indirect method to disable interrupts. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
09ee929ccc
commit
6892914fb7
@ -340,10 +340,12 @@ static struct {
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static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
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{
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spin_lock_bh(&tp->indirect_lock);
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unsigned long flags;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
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spin_unlock_bh(&tp->indirect_lock);
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}
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static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
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@ -352,23 +354,74 @@ static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
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readl(tp->regs + off);
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}
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static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
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pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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return val;
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}
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static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
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{
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unsigned long flags;
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if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
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pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
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TG3_64BIT_REG_LOW, val);
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return;
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}
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if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
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pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
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TG3_64BIT_REG_LOW, val);
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return;
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}
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spin_lock_irqsave(&tp->indirect_lock, flags);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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/* In indirect mode when disabling interrupts, we also need
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* to clear the interrupt bit in the GRC local ctrl register.
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*/
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if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
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(val == 0x1)) {
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pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
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tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
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}
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}
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static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
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pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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return val;
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}
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static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
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{
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if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
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spin_lock_bh(&tp->indirect_lock);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
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pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
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spin_unlock_bh(&tp->indirect_lock);
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} else {
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void __iomem *dest = tp->regs + off;
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writel(val, dest);
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readl(dest); /* always flush PCI write */
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}
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tp->write32(tp, off, val);
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if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
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!(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
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!(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
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tp->read32(tp, off); /* flush */
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}
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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tp->write32_mbox(tp, off, val);
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if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
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!(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
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tp->read32_mbox(tp, off);
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}
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@ -404,24 +457,28 @@ static u32 tg3_read32(struct tg3 *tp, u32 off)
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static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
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{
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spin_lock_bh(&tp->indirect_lock);
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unsigned long flags;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
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pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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/* Always leave this as zero. */
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pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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spin_unlock_bh(&tp->indirect_lock);
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}
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static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
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{
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spin_lock_bh(&tp->indirect_lock);
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unsigned long flags;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
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pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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/* Always leave this as zero. */
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pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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spin_unlock_bh(&tp->indirect_lock);
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}
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static void tg3_disable_ints(struct tg3 *tp)
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@ -9149,14 +9206,6 @@ static int __devinit tg3_is_sun_570X(struct tg3 *tp)
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static int __devinit tg3_get_invariants(struct tg3 *tp)
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{
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static struct pci_device_id write_reorder_chipsets[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801AA_8) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801AB_8) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801BA_11) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801BA_6) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_FE_GATE_700C) },
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{ },
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@ -9173,7 +9222,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
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#endif
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/* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
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/* If we have an AMD 762 chipset, write
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* reordering to the mailbox registers done by the host
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* controller can cause major troubles. We read back from
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* every mailbox register write to force the writes to be
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@ -9211,6 +9260,69 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
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tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
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/* If we have 5702/03 A1 or A2 on certain ICH chipsets,
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* we need to disable memory and use config. cycles
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* only to access all registers. The 5702/03 chips
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* can mistakenly decode the special cycles from the
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* ICH chipsets as memory write cycles, causing corruption
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* of register and memory space. Only certain ICH bridges
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* will drive special cycles with non-zero data during the
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* address phase which can fall within the 5703's address
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* range. This is not an ICH bug as the PCI spec allows
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* non-zero address during special cycles. However, only
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* these ICH bridges are known to drive non-zero addresses
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* during special cycles.
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*
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* Since special cycles do not cross PCI bridges, we only
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* enable this workaround if the 5703 is on the secondary
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* bus of these ICH bridges.
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*/
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if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
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(tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
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static struct tg3_dev_id {
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u32 vendor;
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u32 device;
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u32 rev;
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} ich_chipsets[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
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PCI_ANY_ID },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
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PCI_ANY_ID },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
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0xa },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
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PCI_ANY_ID },
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{ },
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};
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struct tg3_dev_id *pci_id = &ich_chipsets[0];
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struct pci_dev *bridge = NULL;
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while (pci_id->vendor != 0) {
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bridge = pci_get_device(pci_id->vendor, pci_id->device,
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bridge);
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if (!bridge) {
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pci_id++;
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continue;
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}
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if (pci_id->rev != PCI_ANY_ID) {
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u8 rev;
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pci_read_config_byte(bridge, PCI_REVISION_ID,
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&rev);
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if (rev > pci_id->rev)
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continue;
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}
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if (bridge->subordinate &&
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(bridge->subordinate->number ==
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tp->pdev->bus->number)) {
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tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
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pci_dev_put(bridge);
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break;
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}
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}
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}
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/* Find msi capability. */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
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tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
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@ -9342,6 +9454,22 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->write32_rx_mbox = tg3_write_flush_reg32;
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}
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if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
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tp->read32 = tg3_read_indirect_reg32;
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tp->write32 = tg3_write_indirect_reg32;
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tp->read32_mbox = tg3_read_indirect_mbox;
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tp->write32_mbox = tg3_write_indirect_mbox;
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tp->write32_tx_mbox = tg3_write_indirect_mbox;
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tp->write32_rx_mbox = tg3_write_indirect_mbox;
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iounmap(tp->regs);
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tp->regs = 0;
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pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
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pci_cmd &= ~PCI_COMMAND_MEMORY;
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pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
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}
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
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* determined before calling tg3_set_power_state() so that
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@ -10486,7 +10614,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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return 0;
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err_out_iounmap:
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if (tp->regs) {
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iounmap(tp->regs);
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tp->regs = 0;
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}
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err_out_free_dev:
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free_netdev(dev);
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@ -10508,7 +10639,10 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
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struct tg3 *tp = netdev_priv(dev);
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unregister_netdev(dev);
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if (tp->regs) {
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iounmap(tp->regs);
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tp->regs = 0;
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}
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free_netdev(dev);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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@ -2174,6 +2174,7 @@ struct tg3 {
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#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
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TG3_FLG2_MII_SERDES)
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#define TG3_FLG2_PARALLEL_DETECT 0x01000000
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#define TG3_FLG2_ICH_WORKAROUND 0x02000000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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