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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/radeon/hdmi: DCE2: update setmode
Recent RE efforts revealed ops performed by fglrx during HDMI setup. This mostly adds masks to r/w ops plus few single missing bits. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rafał Miłecki
Alex Deucher
parent
2e93cac90c
commit
68706337da
@ -142,14 +142,26 @@ void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
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WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
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WREG32_P(HDMI0_ACR_32_0 + offset,
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HDMI0_ACR_CTS_32(acr.cts_32khz),
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~HDMI0_ACR_CTS_32_MASK);
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WREG32_P(HDMI0_ACR_32_1 + offset,
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HDMI0_ACR_N_32(acr.n_32khz),
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~HDMI0_ACR_N_32_MASK);
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WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
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WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
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WREG32_P(HDMI0_ACR_44_0 + offset,
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HDMI0_ACR_CTS_44(acr.cts_44_1khz),
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~HDMI0_ACR_CTS_44_MASK);
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WREG32_P(HDMI0_ACR_44_1 + offset,
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HDMI0_ACR_N_44(acr.n_44_1khz),
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~HDMI0_ACR_N_44_MASK);
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WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
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WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
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WREG32_P(HDMI0_ACR_48_0 + offset,
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HDMI0_ACR_CTS_48(acr.cts_48khz),
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~HDMI0_ACR_CTS_48_MASK);
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WREG32_P(HDMI0_ACR_48_1 + offset,
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HDMI0_ACR_N_48(acr.n_48khz),
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~HDMI0_ACR_N_48_MASK);
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}
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/*
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@ -349,39 +361,44 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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r600_audio_set_dto(encoder, mode->clock);
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND); /* send null packets when required */
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WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
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HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
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HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
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~(HDMI0_AUDIO_SAMPLE_SEND |
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HDMI0_AUDIO_DELAY_EN_MASK |
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HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
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HDMI0_60958_CS_UPDATE));
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/* DCE 3.0 uses register that's normally for CRC_CONTROL */
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acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
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HDMI0_ACR_PACKET_CONTROL;
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WREG32(acr_ctl + offset,
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HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
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HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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WREG32_P(acr_ctl + offset,
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HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
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HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
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~(HDMI0_ACR_SOURCE |
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HDMI0_ACR_AUTO_SEND));
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND | /* send null packets when required */
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HDMI0_GC_SEND | /* send general control packets */
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HDMI0_GC_CONT); /* send general control packets every frame */
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WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND | /* send null packets when required */
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HDMI0_GC_SEND | /* send general control packets */
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HDMI0_GC_CONT); /* send general control packets every frame */
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/* TODO: HDMI0_AUDIO_INFO_UPDATE */
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WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
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HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
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HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
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HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
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WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
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HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
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HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
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HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
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WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
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HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
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HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
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WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
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HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
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HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
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~(HDMI0_AVI_INFO_LINE_MASK |
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HDMI0_AUDIO_INFO_LINE_MASK));
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WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
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WREG32_AND(HDMI0_GC + offset,
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~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
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err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
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if (err < 0) {
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@ -396,8 +413,29 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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}
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r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
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/* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
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WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
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~(HDMI0_GENERIC0_SEND |
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HDMI0_GENERIC0_CONT |
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HDMI0_GENERIC0_UPDATE |
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HDMI0_GENERIC1_SEND |
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HDMI0_GENERIC1_CONT |
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HDMI0_GENERIC0_LINE_MASK |
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HDMI0_GENERIC1_LINE_MASK));
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r600_hdmi_update_ACR(encoder, mode->clock);
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WREG32_P(HDMI0_60958_0 + offset,
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HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
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~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
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HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
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WREG32_P(HDMI0_60958_1 + offset,
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HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
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~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
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/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
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WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
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WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
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@ -1029,9 +1029,11 @@
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#define HDMI0_AUDIO_PACKET_CONTROL 0x7408
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# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)
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# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
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# define HDMI0_AUDIO_DELAY_EN_MASK (3 << 4)
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# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)
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# define HDMI0_AUDIO_TEST_EN (1 << 12)
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# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
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# define HDMI0_AUDIO_PACKETS_PER_LINE_MASK (0x1f << 16)
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# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)
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# define HDMI0_60958_CS_UPDATE (1 << 26)
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# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)
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@ -1055,7 +1057,9 @@
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# define HDMI0_MPEG_INFO_UPDATE (1 << 10)
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#define HDMI0_INFOFRAME_CONTROL1 0x7418
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# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
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# define HDMI0_AVI_INFO_LINE_MASK (0x3f << 0)
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# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
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# define HDMI0_AUDIO_INFO_LINE_MASK (0x3f << 8)
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# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
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#define HDMI0_GENERIC_PACKET_CONTROL 0x741c
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# define HDMI0_GENERIC0_SEND (1 << 0)
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@ -1064,7 +1068,9 @@
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# define HDMI0_GENERIC1_SEND (1 << 4)
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# define HDMI0_GENERIC1_CONT (1 << 5)
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# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
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# define HDMI0_GENERIC0_LINE_MASK (0x3f << 16)
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# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
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# define HDMI0_GENERIC1_LINE_MASK (0x3f << 24)
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#define HDMI0_GC 0x7428
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# define HDMI0_GC_AVMUTE (1 << 0)
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#define HDMI0_AVI_INFO0 0x7454
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@ -1120,16 +1126,22 @@
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#define HDMI0_GENERIC1_6 0x74a8
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#define HDMI0_ACR_32_0 0x74ac
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# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
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# define HDMI0_ACR_CTS_32_MASK (0xfffff << 12)
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#define HDMI0_ACR_32_1 0x74b0
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# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)
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# define HDMI0_ACR_N_32_MASK (0xfffff << 0)
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#define HDMI0_ACR_44_0 0x74b4
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# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
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# define HDMI0_ACR_CTS_44_MASK (0xfffff << 12)
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#define HDMI0_ACR_44_1 0x74b8
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# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)
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# define HDMI0_ACR_N_44_MASK (0xfffff << 0)
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#define HDMI0_ACR_48_0 0x74bc
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# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
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# define HDMI0_ACR_CTS_48_MASK (0xfffff << 12)
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#define HDMI0_ACR_48_1 0x74c0
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# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)
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# define HDMI0_ACR_N_48_MASK (0xfffff << 0)
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#define HDMI0_ACR_STATUS_0 0x74c4
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#define HDMI0_ACR_STATUS_1 0x74c8
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#define HDMI0_AUDIO_INFO0 0x74cc
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@ -1149,14 +1161,17 @@
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# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
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# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
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# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
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# define HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK (0xf << 20)
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# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
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# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
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# define HDMI0_60958_CS_CLOCK_ACCURACY_MASK (3 << 28)
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#define HDMI0_60958_1 0x74d8
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# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
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# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
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# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)
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# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)
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# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
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# define HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK (0xf << 20)
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#define HDMI0_ACR_PACKET_CONTROL 0x74dc
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# define HDMI0_ACR_SEND (1 << 0)
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# define HDMI0_ACR_CONT (1 << 1)
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