AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-15 00:16:43 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: dts: meson8: add more L2 cache settings

Browse Source 
Amlogic's vendor kernel prints these PL310 L2 cache controller settings
during boot:
  8 ways, 4096 sets, CACHE_ID 0x4100a0c9,  Cache size: 1048576 B
  AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL  0x00000000
  TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222

Add the "prefetch-data", "prefetch-instr" and "arm,shared-override"
properties to get the same L2 cache controller configuration as the
vendor kernel.
Two differences still remain:
- L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0
driver
- bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2017-10-31 23:23:16 +01:00 committed by Kevin Hilman
parent 9bef306b6b
commit 6844e968b5
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/meson8.dtsi
View File

@ -308,6 +308,9 @@ &L2 {
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
arm,filter-ranges = <0x100000 0xc0000000>;
prefetch-data = <1>;
prefetch-instr = <1>;
arm,shared-override;
};
&pwm_ab {