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drm/amdgpu: pad gfx and compute rings to 256 dw

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The same as on windows to avoid further problems with CE/DE
command submission overlaps.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2016-10-05 12:38:21 +02:00 committed by Alex Deucher
parent ec9aaaff66
commit 66f3b2d527
3 changed files with 6 additions and 6 deletions
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4
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View File

@ -2896,7 +2896,7 @@ static int gfx_v6_0_sw_init(void *handle)
ring->ring_obj = NULL; ring->ring_obj = NULL;
sprintf(ring->name, "gfx"); sprintf(ring->name, "gfx");
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
0x80000000, 0xf, 0x80000000, 0xff,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
AMDGPU_RING_TYPE_GFX); AMDGPU_RING_TYPE_GFX);
if (r) if (r)
@ -2920,7 +2920,7 @@ static int gfx_v6_0_sw_init(void *handle)
sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
0x80000000, 0xf, 0x80000000, 0xff,
&adev->gfx.eop_irq, irq_type, &adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE); AMDGPU_RING_TYPE_COMPUTE);
if (r) if (r)

4
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@ -4646,7 +4646,7 @@ static int gfx_v7_0_sw_init(void *handle)
ring->ring_obj = NULL; ring->ring_obj = NULL;
sprintf(ring->name, "gfx"); sprintf(ring->name, "gfx");
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
PACKET3(PACKET3_NOP, 0x3FFF), 0xf, PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
AMDGPU_RING_TYPE_GFX); AMDGPU_RING_TYPE_GFX);
if (r) if (r)
@ -4673,7 +4673,7 @@ static int gfx_v7_0_sw_init(void *handle)
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
/* type-2 packets are deprecated on MEC, use type-3 instead */ /* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
PACKET3(PACKET3_NOP, 0x3FFF), 0xf, PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, irq_type, &adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE); AMDGPU_RING_TYPE_COMPUTE);
if (r) if (r)

4
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@ -2035,7 +2035,7 @@ static int gfx_v8_0_sw_init(void *handle)
} }
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
PACKET3(PACKET3_NOP, 0x3FFF), 0xf, PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
AMDGPU_RING_TYPE_GFX); AMDGPU_RING_TYPE_GFX);
if (r) if (r)
@ -2062,7 +2062,7 @@ static int gfx_v8_0_sw_init(void *handle)
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
/* type-2 packets are deprecated on MEC, use type-3 instead */ /* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
PACKET3(PACKET3_NOP, 0x3FFF), 0xf, PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, irq_type, &adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE); AMDGPU_RING_TYPE_COMPUTE);
if (r) if (r)