AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-02-17 11:17:25 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: tegra: support for Tegra30 CPU powerdomains

Browse Source 
Secondary CPU powerdomains can be powergated on Tegra30. Add the necessary
functions to do this. This will be used to boot the secondary CPUs later on.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Peter De Schrijver 2012-02-10 01:47:49 +02:00 committed by Olof Johansson
parent 6cafa97d3c
commit 65fe31da5c
3 changed files with 24 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-tegra/common.c
View File

@ -28,6 +28,7 @@
#include <mach/iomap.h>
#include <mach/system.h>
#include <mach/powergate.h>
#include "board.h"
#include "clock.h"
@ -119,6 +120,7 @@ void __init tegra20_init_early(void)
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441);
tegra_pmc_init();
tegra_powergate_init();
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
@ -128,5 +130,6 @@ void __init tegra30_init_early(void)
tegra30_init_clocks();
tegra_init_cache(0x441, 0x551);
tegra_pmc_init();
tegra_powergate_init();
}
#endif

3
arch/arm/mach-tegra/include/mach/powergate.h
View File

@ -38,6 +38,9 @@
#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
int __init tegra_powergate_init(void);
int tegra_cpu_powergate_id(int cpuid);
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);

19
arch/arm/mach-tegra/powergate.c
View File

@ -41,6 +41,14 @@
#define PWRGATE_STATUS 0x38
static int tegra_num_powerdomains;
static int tegra_num_cpu_domains;
static u8 *tegra_cpu_domains;
static u8 tegra30_cpu_domains[] = {
TEGRA_POWERGATE_CPU0,
TEGRA_POWERGATE_CPU1,
TEGRA_POWERGATE_CPU2,
TEGRA_POWERGATE_CPU3,
};
static DEFINE_SPINLOCK(tegra_powergate_lock);
@ -161,6 +169,14 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
return ret;
}
int tegra_cpu_powergate_id(int cpuid)
{
if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
return tegra_cpu_domains[cpuid];
return -EINVAL;
}
int __init tegra_powergate_init(void)
{
switch (tegra_chip_id) {
@ -169,6 +185,8 @@ int __init tegra_powergate_init(void)
break;
case TEGRA30:
tegra_num_powerdomains = 14;
tegra_num_cpu_domains = 4;
tegra_cpu_domains = tegra30_cpu_domains;
break;
default:
/* Unknown Tegra variant. Disable powergating */
@ -178,7 +196,6 @@ int __init tegra_powergate_init(void)
return 0;
}
arch_initcall(tegra_powergate_init);
#ifdef CONFIG_DEBUG_FS