mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 14:40:55 +07:00
ARM: dts: omap3 clock data
This patch creates a unique node for each clock in the OMAP3 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tero Kristo
Mike Turquette
parent
ea291c9851
commit
657fc11cca
128
arch/arm/boot/dts/am35xx-clocks.dtsi
Normal file
128
arch/arm/boot/dts/am35xx-clocks.dtsi
Normal file
@ -0,0 +1,128 @@
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/*
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* Device Tree Source for OMAP3 clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm_clocks {
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emac_ick: emac_ick {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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clocks = <&ipss_ick>;
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reg = <0x059c>;
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ti,bit-shift = <1>;
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};
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emac_fck: emac_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&rmii_ck>;
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reg = <0x059c>;
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ti,bit-shift = <9>;
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};
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vpfe_ick: vpfe_ick {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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clocks = <&ipss_ick>;
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reg = <0x059c>;
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ti,bit-shift = <2>;
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};
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vpfe_fck: vpfe_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&pclk_ck>;
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reg = <0x059c>;
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ti,bit-shift = <10>;
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};
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hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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clocks = <&ipss_ick>;
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reg = <0x059c>;
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ti,bit-shift = <0>;
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};
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hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_ck>;
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reg = <0x059c>;
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ti,bit-shift = <8>;
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};
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hecc_ck: hecc_ck {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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clocks = <&sys_ck>;
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reg = <0x059c>;
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ti,bit-shift = <3>;
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};
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};
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&cm_clocks {
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ipss_ick: ipss_ick {
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#clock-cells = <0>;
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compatible = "ti,am35xx-interface-clock";
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clocks = <&core_l3_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <4>;
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};
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rmii_ck: rmii_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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pclk_ck: pclk_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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};
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uart4_ick_am35xx: uart4_ick_am35xx {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <23>;
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};
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uart4_fck_am35xx: uart4_fck_am35xx {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <23>;
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};
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};
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&cm_clockdomains {
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
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<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
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<&hecc_ck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
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<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
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<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
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};
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};
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@ -89,6 +89,45 @@ aes: aes@480c5000 {
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interrupts = <0>;
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};
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prm: prm@48306000 {
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compatible = "ti,omap3-prm";
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reg = <0x48306000 0x4000>;
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prm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prm_clockdomains: clockdomains {
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};
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};
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cm: cm@48004000 {
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compatible = "ti,omap3-cm";
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reg = <0x48004000 0x4000>;
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cm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_clockdomains: clockdomains {
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};
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};
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scrm: scrm@48002000 {
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compatible = "ti,omap3-scrm";
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reg = <0x48002000 0x2000>;
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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counter32k: counter@48320000 {
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compatible = "ti,omap-counter32k";
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reg = <0x48320000 0x20>;
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@ -632,3 +671,5 @@ usb_otg_hs: usb_otg_hs@480ab000 {
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};
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};
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};
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/include/ "omap3xxx-clocks.dtsi"
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208
arch/arm/boot/dts/omap3430es1-clocks.dtsi
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208
arch/arm/boot/dts/omap3430es1-clocks.dtsi
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@ -0,0 +1,208 @@
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/*
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* Device Tree Source for OMAP3430 ES1 clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cm_clocks {
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gfx_l3_ck: gfx_l3_ck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&l3_ick>;
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reg = <0x0b10>;
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ti,bit-shift = <0>;
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};
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gfx_l3_fck: gfx_l3_fck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&l3_ick>;
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ti,max-div = <7>;
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reg = <0x0b40>;
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ti,index-starts-at-one;
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};
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gfx_l3_ick: gfx_l3_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&gfx_l3_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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gfx_cg1_ck: gfx_cg1_ck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&gfx_l3_fck>;
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reg = <0x0b00>;
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ti,bit-shift = <1>;
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};
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gfx_cg2_ck: gfx_cg2_ck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&gfx_l3_fck>;
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reg = <0x0b00>;
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ti,bit-shift = <2>;
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};
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d2d_26m_fck: d2d_26m_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0a00>;
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ti,bit-shift = <3>;
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};
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fshostusb_fck: fshostusb_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <5>;
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};
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ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <0>;
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reg = <0x0a00>;
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};
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ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
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};
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ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&ssi_ssr_fck_3430es1>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&core_l3_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <4>;
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};
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fac_ick: fac_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <8>;
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};
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ssi_l4_ick: ssi_l4_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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ssi_ick_3430es1: ssi_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&ssi_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <0>;
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};
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usb_l4_gate_ick: usb_l4_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <5>;
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reg = <0x0a10>;
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};
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usb_l4_div_ick: usb_l4_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <4>;
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ti,max-div = <1>;
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reg = <0x0a40>;
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ti,index-starts-at-one;
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};
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usb_l4_ick: usb_l4_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
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};
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dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0e00>;
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ti,set-rate-parent;
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};
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dss_ick_3430es1: dss_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&l4_ick>;
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reg = <0x0e10>;
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ti,bit-shift = <0>;
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};
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};
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&cm_clockdomains {
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
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};
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gfx_3430es1_clkdm: gfx_3430es1_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
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<&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
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};
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d2d_clkdm: d2d_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&d2d_26m_fck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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<&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
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};
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};
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268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
Normal file
268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
Normal file
@ -0,0 +1,268 @@
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/*
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* Device Tree Source for OMAP34XX/OMAP36XX clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
|
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*/
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&cm_clocks {
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security_l4_ick2: security_l4_ick2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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aes1_ick: aes1_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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ti,bit-shift = <3>;
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reg = <0x0a14>;
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};
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rng_ick: rng_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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reg = <0x0a14>;
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ti,bit-shift = <2>;
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};
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sha11_ick: sha11_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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reg = <0x0a14>;
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ti,bit-shift = <1>;
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||||
};
|
||||
|
||||
des1_ick: des1_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cam_mclk: cam_mclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll4_m5x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0f00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
cam_ick: cam_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0f10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
csi2_96m_fck: csi2_96m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0f00>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
security_l3_ick: security_l3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l3_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pka_ick: pka_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l3_ick>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
icr_ick: icr_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <29>;
|
||||
};
|
||||
|
||||
des2_ick: des2_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <26>;
|
||||
};
|
||||
|
||||
mspro_ick: mspro_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
mailboxes_ick: mailboxes_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sr1_fck: sr1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <6>;
|
||||
};
|
||||
|
||||
sr2_fck: sr2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
sr_l4_ick: sr_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll2_fck: dpll2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <19>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0040>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll2_ck: dpll2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&dpll2_fck>;
|
||||
reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
|
||||
ti,low-power-stop;
|
||||
ti,lock;
|
||||
ti,low-power-bypass;
|
||||
};
|
||||
|
||||
dpll2_m2_ck: dpll2_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0044>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
iva2_ck: iva2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&dpll2_m2_ck>;
|
||||
reg = <0x0000>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
modem_fck: modem_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <31>;
|
||||
};
|
||||
|
||||
sad2d_ick: sad2d_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mad2d_ick: mad2d_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mspro_fck: mspro_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
cam_clkdm: cam_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cam_ick>, <&csi2_96m_fck>;
|
||||
};
|
||||
|
||||
iva2_clkdm: iva2_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&iva2_ck>;
|
||||
};
|
||||
|
||||
dpll2_clkdm: dpll2_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll2_ck>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
|
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
|
||||
<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
|
||||
};
|
||||
|
||||
d2d_clkdm: d2d_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
|
||||
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
|
||||
<&mspro_fck>;
|
||||
};
|
||||
};
|
||||
@ -26,3 +26,7 @@ cpu@0 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap34xx-omap36xx-clocks.dtsi"
|
||||
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
Normal file
242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
Normal file
@ -0,0 +1,242 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&prm_clocks {
|
||||
corex2_d3_fck: corex2_d3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <3>;
|
||||
};
|
||||
|
||||
corex2_d5_fck: corex2_d5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <5>;
|
||||
};
|
||||
};
|
||||
&cm_clocks {
|
||||
dpll5_ck: dpll5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
|
||||
ti,low-power-stop;
|
||||
ti,lock;
|
||||
};
|
||||
|
||||
dpll5_m2_ck: dpll5_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll5_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0d50>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
sgx_gate_fck: sgx_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0b00>;
|
||||
};
|
||||
|
||||
core_d3_ck: core_d3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <3>;
|
||||
};
|
||||
|
||||
core_d4_ck: core_d4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
core_d6_ck: core_d6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <6>;
|
||||
};
|
||||
|
||||
omap_192m_alwon_fck: omap_192m_alwon_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll4_m2x2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
core_d2_ck: core_d2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
sgx_mux_fck: sgx_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
|
||||
reg = <0x0b40>;
|
||||
};
|
||||
|
||||
sgx_fck: sgx_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
|
||||
};
|
||||
|
||||
sgx_ick: sgx_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0b10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cpefuse_fck: cpefuse_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ts_fck: ts_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&omap_32k_fck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
usbtll_fck: usbtll_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
usbtll_ick: usbtll_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
mmchs3_ick: mmchs3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
|
||||
mmchs3_fck: mmchs3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0e00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dss_ick_3430es2: dss_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dss-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0e10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usbhost_120m_fck: usbhost_120m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
reg = <0x1400>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
usbhost_48m_fck: usbhost_48m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&omap_48m_fck>;
|
||||
reg = <0x1400>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usbhost_ick: usbhost_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dss-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x1410>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
dpll5_clkdm: dpll5_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll5_ck>;
|
||||
};
|
||||
|
||||
sgx_clkdm: sgx_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sgx_ick>;
|
||||
};
|
||||
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
|
||||
<&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
|
||||
};
|
||||
|
||||
usbhost_clkdm: usbhost_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
|
||||
<&usbhost_ick>;
|
||||
};
|
||||
};
|
||||
90
arch/arm/boot/dts/omap36xx-clocks.dtsi
Normal file
90
arch/arm/boot/dts/omap36xx-clocks.dtsi
Normal file
@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP36xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
dpll4_ck: dpll4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-per-j-type-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
|
||||
};
|
||||
|
||||
dpll4_m5x2_ck: dpll4_m5x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m5x2_mul_ck>;
|
||||
ti,bit-shift = <0x1e>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-rate-parent;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m2x2_ck: dpll4_m2x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll3_m3x2_ck: dpll3_m3x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll3_m3x2_mul_ck>;
|
||||
ti,bit-shift = <0xc>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m3x2_ck: dpll4_m3x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m3x2_mul_ck>;
|
||||
ti,bit-shift = <0x1c>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m6x2_ck: dpll4_m6x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m6x2_mul_ck>;
|
||||
ti,bit-shift = <0x1f>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
uart4_fck: uart4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&per_48m_fck>;
|
||||
reg = <0x1000>;
|
||||
ti,bit-shift = <18>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
dpll4_clkdm: dpll4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll4_ck>;
|
||||
};
|
||||
|
||||
per_clkdm: per_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
|
||||
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
|
||||
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
|
||||
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
|
||||
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
|
||||
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
|
||||
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
|
||||
<&mcbsp4_ick>, <&uart4_fck>;
|
||||
};
|
||||
};
|
||||
198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
Normal file
198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
Normal file
@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP34xx/OMAP36xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0a00>;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
|
||||
ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
|
||||
};
|
||||
|
||||
ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&ssi_ssr_fck_3430es2>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-hsotgusb-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ssi_ick_3430es2: ssi_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usim_gate_fck: usim_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
ti,bit-shift = <9>;
|
||||
reg = <0x0c00>;
|
||||
};
|
||||
|
||||
sys_d2_ck: sys_d2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
omap_96m_d2_fck: omap_96m_d2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
omap_96m_d4_fck: omap_96m_d4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
omap_96m_d8_fck: omap_96m_d8_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
omap_96m_d10_fck: omap_96m_d10_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <10>;
|
||||
};
|
||||
|
||||
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <16>;
|
||||
};
|
||||
|
||||
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <20>;
|
||||
};
|
||||
|
||||
usim_mux_fck: usim_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0c40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usim_fck: usim_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
|
||||
};
|
||||
|
||||
usim_ick: usim_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&wkup_l4_ick>;
|
||||
reg = <0x0c10>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
|
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
|
||||
<&gpt1_ick>, <&usim_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
|
||||
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&ssi_ick_3430es2>;
|
||||
};
|
||||
};
|
||||
@ -40,3 +40,8 @@ uart4: serial@49042000 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap36xx-clocks.dtsi"
|
||||
/include/ "omap34xx-omap36xx-clocks.dtsi"
|
||||
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi
Normal file
1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user