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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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rt2x00: Add rt3090 support in rt2800 register initialization.
Add RT3090 specific register initializations to rt2x00, based on the latest Ralink rt3090 vendor driver. Untested as I don't actually own an RT3090 based device, but given experiences on rt3070/rt3071 very hopeful that this will actually work.. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gertjan van Wingerde
John W. Linville
parent
d5385bfc59
commit
64522957ce
@ -1043,7 +1043,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
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{
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if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
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if (rt2x00_rt(rt2x00dev, RT3070) ||
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rt2x00_rt(rt2x00dev, RT3071))
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rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090))
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return 0x1c + (2 * rt2x00dev->lna_gain);
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else
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return 0x2e + rt2x00dev->lna_gain;
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@ -1192,10 +1193,12 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
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rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
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if (rt2x00_rt(rt2x00dev, RT3071)) {
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if (rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
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rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) {
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
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rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
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rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
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if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
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rt2800_register_write(rt2x00dev, TX_SW_CFG2,
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@ -1558,7 +1561,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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rt2800_bbp_write(rt2x00dev, 70, 0x0a);
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if (rt2x00_rt(rt2x00dev, RT3070) ||
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rt2x00_rt(rt2x00dev, RT3071)) {
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rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_bbp_write(rt2x00dev, 79, 0x13);
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rt2800_bbp_write(rt2x00dev, 80, 0x05);
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rt2800_bbp_write(rt2x00dev, 81, 0x33);
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@ -1580,7 +1584,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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rt2800_bbp_write(rt2x00dev, 92, 0x00);
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if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
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rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E))
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rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
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rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
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rt2800_bbp_write(rt2x00dev, 103, 0xc0);
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else
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rt2800_bbp_write(rt2x00dev, 103, 0x00);
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@ -1588,7 +1593,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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rt2800_bbp_write(rt2x00dev, 105, 0x05);
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rt2800_bbp_write(rt2x00dev, 106, 0x35);
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if (rt2x00_rt(rt2x00dev, RT3071)) {
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if (rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_bbp_read(rt2x00dev, 138, &value);
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rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
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@ -1688,7 +1694,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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u16 eeprom;
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if (!rt2x00_rt(rt2x00dev, RT3070) &&
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!rt2x00_rt(rt2x00dev, RT3071))
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!rt2x00_rt(rt2x00dev, RT3071) &&
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!rt2x00_rt(rt2x00dev, RT3090))
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return 0;
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/*
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@ -1702,7 +1709,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
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if (rt2x00_rt(rt2x00dev, RT3070) ||
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rt2x00_rt(rt2x00dev, RT3071)) {
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rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
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rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
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rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
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@ -1729,7 +1737,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
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rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
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rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
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} else if (rt2x00_rt(rt2x00dev, RT3071)) {
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} else if (rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
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rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
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@ -1738,7 +1747,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
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rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) {
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
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rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
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rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
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if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
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rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
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@ -1756,7 +1766,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
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rt2x00dev->calibration[1] =
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rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
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} else if (rt2x00_rt(rt2x00dev, RT3071)) {
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} else if (rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2x00dev->calibration[0] =
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rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
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rt2x00dev->calibration[1] =
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@ -1780,7 +1791,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_bbp_write(rt2x00dev, 4, bbp);
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
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rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
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rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
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rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
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rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
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rt2800_register_read(rt2x00dev, OPT_14_CSR, ®);
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@ -1789,7 +1801,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) {
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
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rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
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rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
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if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
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rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
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@ -1801,7 +1814,20 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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EEPROM_TXMIXER_GAIN_BG_VAL));
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rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
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if (rt2x00_rt(rt2x00dev, RT3071)) {
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if (rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_bbp_read(rt2x00dev, 138, &bbp);
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rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
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if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
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rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
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if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
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rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
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rt2800_bbp_write(rt2x00dev, 138, bbp);
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}
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if (rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090)) {
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rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
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rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
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