mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 12:16:45 +07:00
OMAP-GPMC driver fixes for v4.1
* Fixed WAITMONITORINGTIME programming to be based on GPMC_CLK instead of GPMC_FCLK. The GPMC clock divider programming is fixed for both synchronous and asynchronous modes. * Allow GPMC's children of default bus type to be populated in the device tree. * Improved DEBUG output data and format. * Prevent writing 1 into reserved bits of GPMC_CONFIG7. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJU+Z36AAoJENJaa9O+djCTdvUP/3a4AxX5cUavSsu9YYMJirL7 9JxUETrQfjkpRLrXDtahchn/nqnBESMMss992ipWBLyT1idQu81I2wztMM6KuQnc iuL8h8lQCctjEBAkKxWkZVORq60NcgRhBivAClUHxxpobA8MnChRwHmrJI8aPGxp /XKogeg5aa99NyRgQo7t4fMg8/KZWyUGtVf21wXhfwyhuV+dP8vUQMvaxXjQqXJ2 r936x1fOT+hA48sScRbcCGFaATmxoNN5Tx8+lfCqXv2JXUt1Y+7FXUtnkiC3nc6Y JLZ9rKeBv45VLf7TMlGJBlQj3o971CahrlxXv3P3i/G/ALoJE1Xyuqto4dJ474N/ hU7OlPyrSZF9J9z/e0uhpteuk7KHq6mgZ7HGh+ytKlFrTocOqTlbO0L/zRvOXXuB Aajcs1PbpG5j0Znha0sYyj33y5UbKnpTxlydffLA7r3wiNUr3fI9+bR5uOsnu+yF OwgJLCeymp1DiqGx3gupTvkJLJJxb7wjMUncGhXt3pRKJEQHBWekOZnI7v4S3tXE r6HjvKoe+ZdQQyUaCb17jOMZ0FLOSsT3XcIqq1xOMzhxP7tSRRQet3hkdL4CgP1E fedp0FintqpUfzBQkRn6JY/UMR2mCCalPMaOF7L/sa5wOWRSjSoXOHa5w6lHQJVB fWZR4/msDvBrVnxuKAci =wtGZ -----END PGP SIGNATURE----- Merge tag 'gpmc-omap-for-v4.1' of git://github.com/rogerq/linux into next/drivers Merge "OMAP-GPMC driver fixes for v4.1" from Roger Quandros: * Fixed WAITMONITORINGTIME programming to be based on GPMC_CLK instead of GPMC_FCLK. The GPMC clock divider programming is fixed for both synchronous and asynchronous modes. * Allow GPMC's children of default bus type to be populated in the device tree. * Improved DEBUG output data and format. * Prevent writing 1 into reserved bits of GPMC_CONFIG7. * tag 'gpmc-omap-for-v4.1' of git://github.com/rogerq/linux: ARM OMAP2+ GPMC: fix programming/showing reserved timing parameters ARM OMAP2+ GPMC: fix WAITMONITORINGTIME divider bug ARM OMAP2+ GPMC: calculate GPMCFCLKDIVIDER based on WAITMONITORINGTIME ARM OMAP2+ GPMC: always program GPMCFCLKDIVIDER ARM OMAP2+ GPMC: change get_gpmc_timing_reg output for DTS ARM OMAP2+ GPMC: fix debug output alignment ARM OMAP2+ GPMC: add bus children ARM OMAP2+ GPMC: don't undef DEBUG ARM: OMAP2+: gpmc: make gpmc_cs_get_name() static ARM: OMAP2+: gpmc: Fix writing in gpmc_cs_set_memconf Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
63fad06a27
@ -96,14 +96,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
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gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
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if (gpmc_t) {
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err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
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if (err < 0) {
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pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
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return err;
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}
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}
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memset(&s, 0, sizeof(struct gpmc_settings));
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if (gpmc_nand_data->of_node)
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gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
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@ -111,6 +103,16 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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gpmc_set_legacy(gpmc_nand_data, &s);
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s.device_nand = true;
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if (gpmc_t) {
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err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s);
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if (err < 0) {
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pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n",
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err);
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return err;
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}
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}
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err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
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if (err < 0)
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goto out_free_cs;
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@ -293,7 +293,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
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if (ret < 0)
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return ret;
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@ -331,7 +331,7 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
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if (ret < 0)
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return ret;
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@ -71,7 +71,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
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gpmc_calc_timings(&t, &tusb_async, &dev_t);
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return gpmc_cs_set_timings(async_cs, &t);
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return gpmc_cs_set_timings(async_cs, &t, &tusb_async);
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}
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static int tusb_set_sync_mode(unsigned sysclk_ps)
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@ -98,7 +98,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
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gpmc_calc_timings(&t, &tusb_sync, &dev_t);
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return gpmc_cs_set_timings(sync_cs, &t);
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return gpmc_cs_set_timings(sync_cs, &t, &tusb_sync);
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}
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/* tusb driver calls this when it changes the chip's clocking */
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@ -12,8 +12,6 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -29,6 +27,7 @@
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#include <linux/of_address.h>
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#include <linux/of_mtd.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/omap-gpmc.h>
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#include <linux/mtd/nand.h>
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#include <linux/pm_runtime.h>
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@ -136,13 +135,21 @@
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#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
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#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
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#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
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/** CLKACTIVATIONTIME Max Ticks */
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#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
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#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
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/** ATTACHEDDEVICEPAGELENGTH Max Value */
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#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
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#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
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#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
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#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
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#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
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/** WAITMONITORINGTIME Max Ticks */
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#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
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#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
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/** DEVICESIZE Max Value */
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#define GPMC_CONFIG1_DEVICESIZE_MAX 1
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#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
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#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
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#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
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@ -153,6 +160,15 @@
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#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
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#define GPMC_CONFIG7_CSVALID (1 << 6)
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#define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
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#define GPMC_CONFIG7_CSVALID_MASK BIT(6)
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#define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
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#define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
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/* All CONFIG7 bits except reserved bits */
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#define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
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GPMC_CONFIG7_CSVALID_MASK | \
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GPMC_CONFIG7_MASKADDRESS_MASK)
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#define GPMC_DEVICETYPE_NOR 0
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#define GPMC_DEVICETYPE_NAND 2
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#define GPMC_CONFIG_WRITEPROTECT 0x00000010
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@ -169,6 +185,11 @@
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*/
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#define GPMC_NR_IRQ 2
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enum gpmc_clk_domain {
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GPMC_CD_FCLK,
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GPMC_CD_CLK
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};
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struct gpmc_cs_data {
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const char *name;
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@ -267,16 +288,55 @@ static unsigned long gpmc_get_fclk_period(void)
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return rate;
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}
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static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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/**
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* gpmc_get_clk_period - get period of selected clock domain in ps
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* @cs Chip Select Region.
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* @cd Clock Domain.
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*
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* GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
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* prior to calling this function with GPMC_CD_CLK.
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*/
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static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
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{
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unsigned long tick_ps = gpmc_get_fclk_period();
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u32 l;
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int div;
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switch (cd) {
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case GPMC_CD_CLK:
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/* get current clk divider */
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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div = (l & 0x03) + 1;
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/* get GPMC_CLK period */
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tick_ps *= div;
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break;
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case GPMC_CD_FCLK:
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/* FALL-THROUGH */
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default:
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break;
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}
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return tick_ps;
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}
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static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
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enum gpmc_clk_domain cd)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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tick_ps = gpmc_get_clk_period(cs, cd);
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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{
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return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
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}
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static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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{
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unsigned long tick_ps;
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@ -287,9 +347,15 @@ static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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return (time_ps + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
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enum gpmc_clk_domain cd)
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{
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return ticks * gpmc_get_clk_period(cs, cd) / 1000;
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}
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unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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{
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return ticks * gpmc_get_fclk_period() / 1000;
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return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
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}
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static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
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@ -338,33 +404,66 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
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}
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#ifdef DEBUG
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static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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bool raw, bool noval, int shift,
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const char *name)
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/**
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* get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
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* @cs: Chip Select Region
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* @reg: GPMC_CS_CONFIGn register offset.
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* @st_bit: Start Bit
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* @end_bit: End Bit. Must be >= @st_bit.
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* @ma:x Maximum parameter value (before optional @shift).
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* If 0, maximum is as high as @st_bit and @end_bit allow.
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* @name: DTS node name, w/o "gpmc,"
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* @cd: Clock Domain of timing parameter.
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* @shift: Parameter value left shifts @shift, which is then printed instead of value.
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* @raw: Raw Format Option.
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* raw format: gpmc,name = <value>
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* tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
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* Where x ns -- y ns result in the same tick value.
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* When @max is exceeded, "invalid" is printed inside comment.
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* @noval: Parameter values equal to 0 are not printed.
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* @return: Specified timing parameter (after optional @shift).
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*
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*/
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static int get_gpmc_timing_reg(
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/* timing specifiers */
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int cs, int reg, int st_bit, int end_bit, int max,
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const char *name, const enum gpmc_clk_domain cd,
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/* value transform */
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int shift,
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/* format specifiers */
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bool raw, bool noval)
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{
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u32 l;
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int nr_bits, max_value, mask;
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int nr_bits;
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int mask;
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bool invalid;
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l = gpmc_cs_read_reg(cs, reg);
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nr_bits = end_bit - st_bit + 1;
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max_value = (1 << nr_bits) - 1;
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mask = max_value << st_bit;
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l = (l & mask) >> st_bit;
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mask = (1 << nr_bits) - 1;
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l = (l >> st_bit) & mask;
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if (!max)
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max = mask;
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invalid = l > max;
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if (shift)
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l = (shift << l);
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if (noval && (l == 0))
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return 0;
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if (!raw) {
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unsigned int time_ns_min, time_ns, time_ns_max;
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/* DTS tick format for timings in ns */
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unsigned int time_ns;
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unsigned int time_ns_min = 0;
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time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0);
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time_ns = gpmc_ticks_to_ns(l);
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time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ?
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max_value : l + 1);
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pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n",
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name, time_ns, time_ns_min, time_ns_max, l);
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if (l)
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time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
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time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
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pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
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name, time_ns, time_ns_min, time_ns, l,
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invalid ? "; invalid " : " ");
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} else {
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pr_info("gpmc,%s = <%u>\n", name, l);
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/* raw format */
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pr_info("gpmc,%s = <%u>%s\n", name, l,
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invalid ? " /* invalid */" : "");
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}
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return l;
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@ -374,13 +473,19 @@ static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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pr_info("cs%i %s: 0x%08x\n", cs, #config, \
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gpmc_cs_read_reg(cs, config))
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#define GPMC_GET_RAW(reg, st, end, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
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#define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
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#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
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#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
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#define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
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#define GPMC_GET_TICKS(reg, st, end, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
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#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
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#define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
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static void gpmc_show_regs(int cs, const char *desc)
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{
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@ -404,11 +509,14 @@ static void gpmc_cs_show_timings(int cs, const char *desc)
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pr_info("gpmc cs%i access configuration:\n", cs);
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GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
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GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
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GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
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GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
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GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
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GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
|
||||
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
|
||||
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
|
||||
GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length");
|
||||
GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
|
||||
GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
|
||||
"burst-length");
|
||||
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
|
||||
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
|
||||
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
|
||||
@ -448,8 +556,12 @@ static void gpmc_cs_show_timings(int cs, const char *desc)
|
||||
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
|
||||
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
|
||||
|
||||
GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
|
||||
GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
|
||||
GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
|
||||
GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
|
||||
"wait-monitoring-ns", GPMC_CD_CLK);
|
||||
GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
|
||||
GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
|
||||
"clk-activation-ns", GPMC_CD_FCLK);
|
||||
|
||||
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
|
||||
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
|
||||
@ -460,8 +572,24 @@ static inline void gpmc_cs_show_timings(int cs, const char *desc)
|
||||
}
|
||||
#endif
|
||||
|
||||
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
|
||||
int time, const char *name)
|
||||
/**
|
||||
* set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
|
||||
* Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
|
||||
* prior to calling this function with @cd equal to GPMC_CD_CLK.
|
||||
*
|
||||
* @cs: Chip Select Region.
|
||||
* @reg: GPMC_CS_CONFIGn register offset.
|
||||
* @st_bit: Start Bit
|
||||
* @end_bit: End Bit. Must be >= @st_bit.
|
||||
* @max: Maximum parameter value.
|
||||
* If 0, maximum is as high as @st_bit and @end_bit allow.
|
||||
* @time: Timing parameter in ns.
|
||||
* @cd: Timing parameter clock domain.
|
||||
* @name: Timing parameter name.
|
||||
* @return: 0 on success, -1 on error.
|
||||
*/
|
||||
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
|
||||
int time, enum gpmc_clk_domain cd, const char *name)
|
||||
{
|
||||
u32 l;
|
||||
int ticks, mask, nr_bits;
|
||||
@ -469,22 +597,25 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
|
||||
if (time == 0)
|
||||
ticks = 0;
|
||||
else
|
||||
ticks = gpmc_ns_to_ticks(time);
|
||||
ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
|
||||
nr_bits = end_bit - st_bit + 1;
|
||||
mask = (1 << nr_bits) - 1;
|
||||
|
||||
if (ticks > mask) {
|
||||
pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
|
||||
__func__, cs, name, time, ticks, mask);
|
||||
if (!max)
|
||||
max = mask;
|
||||
|
||||
if (ticks > max) {
|
||||
pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
|
||||
__func__, cs, name, time, ticks, max);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
l = gpmc_cs_read_reg(cs, reg);
|
||||
#ifdef DEBUG
|
||||
printk(KERN_INFO
|
||||
"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
|
||||
cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
|
||||
pr_info(
|
||||
"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
|
||||
cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
|
||||
(l >> st_bit) & mask, time);
|
||||
#endif
|
||||
l &= ~(mask << st_bit);
|
||||
@ -494,18 +625,56 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define GPMC_SET_ONE(reg, st, end, field) \
|
||||
if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
|
||||
t->field, #field) < 0) \
|
||||
#define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
|
||||
if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
|
||||
t->field, (cd), #field) < 0) \
|
||||
return -1
|
||||
|
||||
#define GPMC_SET_ONE(reg, st, end, field) \
|
||||
GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
|
||||
|
||||
/**
|
||||
* gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
|
||||
* WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
|
||||
* read --> don't sample bus too early
|
||||
* write --> data is longer on bus
|
||||
*
|
||||
* Formula:
|
||||
* gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
|
||||
* / waitmonitoring_ticks)
|
||||
* WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
|
||||
* div <= 0 check.
|
||||
*
|
||||
* @wait_monitoring: WAITMONITORINGTIME in ns.
|
||||
* @return: -1 on failure to scale, else proper divider > 0.
|
||||
*/
|
||||
static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
|
||||
{
|
||||
|
||||
int div = gpmc_ns_to_ticks(wait_monitoring);
|
||||
|
||||
div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
|
||||
div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
|
||||
|
||||
if (div > 4)
|
||||
return -1;
|
||||
if (div <= 0)
|
||||
div = 1;
|
||||
|
||||
return div;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
|
||||
* @sync_clk: GPMC_CLK period in ps.
|
||||
* @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
|
||||
* Else, returns -1.
|
||||
*/
|
||||
int gpmc_calc_divider(unsigned int sync_clk)
|
||||
{
|
||||
int div;
|
||||
u32 l;
|
||||
int div = gpmc_ps_to_ticks(sync_clk);
|
||||
|
||||
l = sync_clk + (gpmc_get_fclk_period() - 1);
|
||||
div = l / gpmc_get_fclk_period();
|
||||
if (div > 4)
|
||||
return -1;
|
||||
if (div <= 0)
|
||||
@ -514,7 +683,15 @@ int gpmc_calc_divider(unsigned int sync_clk)
|
||||
return div;
|
||||
}
|
||||
|
||||
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
|
||||
/**
|
||||
* gpmc_cs_set_timings - program timing parameters for Chip Select Region.
|
||||
* @cs: Chip Select Region.
|
||||
* @t: GPMC timing parameters.
|
||||
* @s: GPMC timing settings.
|
||||
* @return: 0 on success, -1 on error.
|
||||
*/
|
||||
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
|
||||
const struct gpmc_settings *s)
|
||||
{
|
||||
int div;
|
||||
u32 l;
|
||||
@ -524,6 +701,33 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
|
||||
if (div < 0)
|
||||
return div;
|
||||
|
||||
/*
|
||||
* See if we need to change the divider for waitmonitoringtime.
|
||||
*
|
||||
* Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
|
||||
* pure asynchronous accesses, i.e. both read and write asynchronous.
|
||||
* However, only do so if WAITMONITORINGTIME is actually used, i.e.
|
||||
* either WAITREADMONITORING or WAITWRITEMONITORING is set.
|
||||
*
|
||||
* This statement must not change div to scale async WAITMONITORINGTIME
|
||||
* to protect mixed synchronous and asynchronous accesses.
|
||||
*
|
||||
* We raise an error later if WAITMONITORINGTIME does not fit.
|
||||
*/
|
||||
if (!s->sync_read && !s->sync_write &&
|
||||
(s->wait_on_read || s->wait_on_write)
|
||||
) {
|
||||
|
||||
div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
|
||||
if (div < 0) {
|
||||
pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
|
||||
__func__,
|
||||
t->wait_monitoring
|
||||
);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
|
||||
@ -546,27 +750,27 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
|
||||
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
|
||||
|
||||
if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
|
||||
if (gpmc_capability & GPMC_HAS_WR_ACCESS)
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
|
||||
|
||||
/* caller is expected to have initialized CONFIG1 to cover
|
||||
* at least sync vs async
|
||||
*/
|
||||
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
|
||||
l &= ~0x03;
|
||||
l |= (div - 1);
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
|
||||
|
||||
GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
|
||||
GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
|
||||
wait_monitoring, GPMC_CD_CLK);
|
||||
GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
|
||||
GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
|
||||
clk_activation, GPMC_CD_FCLK);
|
||||
|
||||
#ifdef DEBUG
|
||||
printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
|
||||
cs, (div * gpmc_get_fclk_period()) / 1000, div);
|
||||
pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
|
||||
cs, (div * gpmc_get_fclk_period()) / 1000, div);
|
||||
#endif
|
||||
l &= ~0x03;
|
||||
l |= (div - 1);
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
|
||||
}
|
||||
|
||||
gpmc_cs_bool_timings(cs, &t->bool_timings);
|
||||
gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
|
||||
@ -586,12 +790,15 @@ static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
|
||||
if (base & (size - 1))
|
||||
return -EINVAL;
|
||||
|
||||
base >>= GPMC_CHUNK_SHIFT;
|
||||
mask = (1 << GPMC_SECTION_SHIFT) - size;
|
||||
mask >>= GPMC_CHUNK_SHIFT;
|
||||
mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
|
||||
|
||||
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
|
||||
l &= ~0x3f;
|
||||
l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
|
||||
l &= ~(0x0f << 8);
|
||||
l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
|
||||
l &= ~GPMC_CONFIG7_MASK;
|
||||
l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
|
||||
l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
|
||||
l |= GPMC_CONFIG7_CSVALID;
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
|
||||
|
||||
@ -656,7 +863,7 @@ static void gpmc_cs_set_name(int cs, const char *name)
|
||||
gpmc->name = name;
|
||||
}
|
||||
|
||||
const char *gpmc_cs_get_name(int cs)
|
||||
static const char *gpmc_cs_get_name(int cs)
|
||||
{
|
||||
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
|
||||
|
||||
@ -1786,7 +1993,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
ret = gpmc_cs_set_timings(cs, &gpmc_t);
|
||||
ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
|
||||
child->name);
|
||||
@ -1802,8 +2009,21 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
|
||||
gpmc_cs_enable_mem(cs);
|
||||
|
||||
no_timings:
|
||||
if (of_platform_device_create(child, NULL, &pdev->dev))
|
||||
return 0;
|
||||
|
||||
/* create platform device, NULL on error or when disabled */
|
||||
if (!of_platform_device_create(child, NULL, &pdev->dev))
|
||||
goto err_child_fail;
|
||||
|
||||
/* is child a common bus? */
|
||||
if (of_match_node(of_default_bus_match_table, child))
|
||||
/* create children and other common bus children */
|
||||
if (of_platform_populate(child, of_default_bus_match_table,
|
||||
NULL, &pdev->dev))
|
||||
goto err_child_fail;
|
||||
|
||||
return 0;
|
||||
|
||||
err_child_fail:
|
||||
|
||||
dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
|
||||
ret = -ENODEV;
|
||||
|
||||
@ -163,7 +163,8 @@ extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
|
||||
|
||||
extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
|
||||
extern int gpmc_calc_divider(unsigned int sync_clk);
|
||||
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
|
||||
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
|
||||
const struct gpmc_settings *s);
|
||||
extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
|
||||
extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
|
||||
extern void gpmc_cs_free(int cs);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user