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drm/amdgpu: switch to amdgpu_ras_late_init for gfx v9 block (v2)

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call helper function in late init phase to handle ras init
for gfx ip block

v2: call ras_late_fini to do clean up when fail to enable interrupt

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2019-08-29 19:15:16 +08:00 committed by Alex Deucher
parent b293e891b0
commit 63fa48db49
1 changed files with 22 additions and 72 deletions
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94
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -4402,7 +4402,6 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
static int gfx_v9_0_ecc_late_init(void *handle) static int gfx_v9_0_ecc_late_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ras_common_if **ras_if = &adev->gfx.ras_if;
struct ras_ih_if ih_info = { struct ras_ih_if ih_info = {
.cb = gfx_v9_0_process_ras_data_cb, .cb = gfx_v9_0_process_ras_data_cb,
}; };
@ -4410,18 +4409,18 @@ static int gfx_v9_0_ecc_late_init(void *handle)
.sysfs_name = "gfx_err_count", .sysfs_name = "gfx_err_count",
.debugfs_name = "gfx_err_inject", .debugfs_name = "gfx_err_inject",
}; };
struct ras_common_if ras_block = {
.block = AMDGPU_RAS_BLOCK__GFX,
.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
.sub_block_index = 0,
.name = "gfx",
};
int r; int r;
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { if (!adev->gfx.ras_if) {
amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
return 0; if (!adev->gfx.ras_if)
return -ENOMEM;
adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->gfx.ras_if->sub_block_index = 0;
strcpy(adev->gfx.ras_if->name, "gfx");
} }
fs_info.head = ih_info.head = *adev->gfx.ras_if;
r = gfx_v9_0_do_edc_gds_workarounds(adev); r = gfx_v9_0_do_edc_gds_workarounds(adev);
if (r) if (r)
@ -4432,71 +4431,22 @@ static int gfx_v9_0_ecc_late_init(void *handle)
if (r) if (r)
return r; return r;
/* handle resume path. */ r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
if (*ras_if) { &fs_info, &ih_info);
/* resend ras TA enable cmd during resume. if (r)
* prepare to handle failure. goto free;
*/
ih_info.head = **ras_if; if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
if (r) { if (r)
if (r == -EAGAIN) { goto late_fini;
/* request a gpu reset. will run again. */
amdgpu_ras_request_reset_on_boot(adev,
AMDGPU_RAS_BLOCK__GFX);
return 0;
}
/* fail to enable ras, cleanup all. */
goto irq;
}
/* enable successfully. continue. */
goto resume;
} }
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
return -ENOMEM;
**ras_if = ras_block;
r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
if (r) {
if (r == -EAGAIN) {
amdgpu_ras_request_reset_on_boot(adev,
AMDGPU_RAS_BLOCK__GFX);
r = 0;
}
goto feature;
}
ih_info.head = **ras_if;
fs_info.head = **ras_if;
r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
if (r)
goto interrupt;
amdgpu_ras_debugfs_create(adev, &fs_info);
r = amdgpu_ras_sysfs_create(adev, &fs_info);
if (r)
goto sysfs;
resume:
r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
if (r)
goto irq;
return 0; return 0;
irq: late_fini:
amdgpu_ras_sysfs_remove(adev, *ras_if); amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
sysfs: free:
amdgpu_ras_debugfs_remove(adev, *ras_if); kfree(adev->gfx.ras_if);
amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
interrupt:
amdgpu_ras_feature_enable(adev, *ras_if, 0);
feature:
kfree(*ras_if);
*ras_if = NULL;
return r; return r;
} }