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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: dts: Add STiH418 SoC support
The STiH418 is advanced UHD 60fps AVC processor with 3D graphic acceleration and quad-core ARM Cortex A9 CPU. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This commit is contained in:
Maxime COQUELIN
Maxime Coquelin
parent
956b42d199
commit
63f3171d5e
348
arch/arm/boot/dts/stih418-clock.dtsi
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348
arch/arm/boot/dts/stih418-clock.dtsi
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@ -0,0 +1,348 @@
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/*
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* Copyright (C) 2015 STMicroelectronics R&D Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/stih418-clks.h>
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "st,stih418-clk", "simple-bus";
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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clock-output-names = "CLK_SYSIN";
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/*
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* A9 PLL.
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*/
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0xffff>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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/*
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* ARM CPU related clocks.
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*/
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clk_m_a9: clk-m-a9@92b0000 {
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#clock-cells = <0>;
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compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
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reg = <0x92b0000 0x10000>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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/*
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* Bootloader initialized system infrastructure clock for
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* serial devices.
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*/
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clk_ext2f_a9: clockgen-c0@13 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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clock-output-names = "clk-s-icn-reg-0";
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};
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clockgen-a@090ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0",
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"clk-ic-lmi1";
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};
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};
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clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
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#clock-cells = <1>;
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compatible = "st,stih407-quadfs660-C", "st,quadfs";
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-fs0-ch0",
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"clk-s-c0-fs0-ch1",
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"clk-s-c0-fs0-ch2",
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"clk-s-c0-fs0-ch3";
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};
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clk_s_c0: clockgen-c@09103000 {
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compatible = "st,clkgen-c32";
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reg = <0x9103000 0x1000>;
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clk_s_c0_pll0: clk-s-c0-pll0 {
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#clock-cells = <1>;
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compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll0-odf-0";
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};
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clk_s_c0_pll1: clk-s-c0-pll1 {
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#clock-cells = <1>;
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compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll1-odf-0";
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};
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-icn-reg",
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"clk-proc-bdisp-0",
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"clk-proc-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phyref",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp",
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"clk-tx-icn-hades",
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"clk-rx-icn-hades",
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"clk-icn-reg-16",
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"clk-pp-hevc",
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"clk-clust-hevc",
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"clk-hwpe-hevc",
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"clk-fc-hevc",
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"clk-proc-mixer",
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"clk-proc-sc",
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"clk-avsp-hevc";
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};
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};
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clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
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#clock-cells = <1>;
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compatible = "st,stih407-quadfs660-D", "st,quadfs";
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reg = <0x9104000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d0-fs0-ch0",
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"clk-s-d0-fs0-ch1",
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"clk-s-d0-fs0-ch2",
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"clk-s-d0-fs0-ch3";
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};
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clockgen-d0@09104000 {
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compatible = "st,clkgen-c32";
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reg = <0x9104000 0x1000>;
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clk_s_d0_flexgen: clk-s-d0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_d0_quadfs 0>,
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<&clk_s_d0_quadfs 1>,
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<&clk_s_d0_quadfs 2>,
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<&clk_s_d0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-pcm-0",
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"clk-pcm-1",
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"clk-pcm-2",
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"clk-spdiff",
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"clk-pcmr10-master",
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"clk-usb2-phy";
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};
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};
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clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
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#clock-cells = <1>;
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compatible = "st,stih407-quadfs660-D", "st,quadfs";
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reg = <0x9106000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d2-fs0-ch0",
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"clk-s-d2-fs0-ch1",
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"clk-s-d2-fs0-ch2",
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"clk-s-d2-fs0-ch3";
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clockgen-d2@x9106000 {
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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clk_s_d2_flexgen: clk-s-d2-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>,
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<&clk_s_d2_quadfs 2>,
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<&clk_s_d2_quadfs 3>,
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<&clk_sysin>,
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<&clk_sysin>,
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<&clk_tmdsout_hdmi>;
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clock-output-names = "clk-pix-main-disp",
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"",
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"",
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"",
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"",
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"clk-tmds-hdmi-div2",
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"clk-pix-aux-disp",
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"clk-denc",
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"clk-pix-hddac",
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"clk-hddac",
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"clk-sddac",
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"clk-pix-dvo",
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"clk-dvo",
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"clk-pix-hdmi",
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"clk-tmds-hdmi",
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"clk-ref-hdmiphy",
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"", "", "", "", "",
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"", "", "", "", "",
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"", "", "", "", "",
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"", "", "", "", "",
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"", "", "", "", "",
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"", "", "", "", "",
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"", "clk-vp9";
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};
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};
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clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
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#clock-cells = <1>;
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compatible = "st,stih407-quadfs660-D", "st,quadfs";
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reg = <0x9107000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d3-fs0-ch0",
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"clk-s-d3-fs0-ch1",
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"clk-s-d3-fs0-ch2",
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"clk-s-d3-fs0-ch3";
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};
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clockgen-d3@9107000 {
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compatible = "st,clkgen-c32";
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reg = <0x9107000 0x1000>;
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clk_s_d3_flexgen: clk-s-d3-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_d3_quadfs 0>,
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<&clk_s_d3_quadfs 1>,
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<&clk_s_d3_quadfs 2>,
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<&clk_s_d3_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-stfe-frc1",
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"clk-tsout-0",
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"clk-tsout-1",
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"clk-mchi",
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"clk-vsens-compo",
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"clk-frc1-remote",
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"clk-lpc-0",
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"clk-lpc-1";
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};
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};
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};
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};
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99
arch/arm/boot/dts/stih418.dtsi
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99
arch/arm/boot/dts/stih418.dtsi
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@ -0,0 +1,99 @@
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/*
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* Copyright (C) 2014 STMicroelectronics Limited.
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* Author: Peter Griffin <peter.griffin@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih418-clock.dtsi"
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#include "stih407-family.dtsi"
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#include "stih410-pinctrl.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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};
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};
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soc {
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usb2_picophy1: phy2 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xf8 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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};
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usb2_picophy2: phy3 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xfc 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY1_RESET>;
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reset-names = "global", "port";
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};
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ohci0: usb@9a03c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a03c00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ehci0: usb@9a03e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a03e00 0x100>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ohci1: usb@9a83c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a83c00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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ehci1: usb@9a83e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a83e00 0x100>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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};
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};
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34
include/dt-bindings/clock/stih418-clks.h
Normal file
34
include/dt-bindings/clock/stih418-clks.h
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* This header provides constants clk index STMicroelectronics
|
||||
* STiH418 SoC.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_CLK_STIH418
|
||||
#define _DT_BINDINGS_CLK_STIH418
|
||||
|
||||
#include "stih410-clks.h"
|
||||
|
||||
/* STiH418 introduces new clock outputs compared to STiH410 */
|
||||
|
||||
/* CLOCKGEN C0 */
|
||||
#define CLK_PROC_BDISP_0 14
|
||||
#define CLK_PROC_BDISP_1 15
|
||||
#define CLK_TX_ICN_1 23
|
||||
#define CLK_ETH_PHYREF 27
|
||||
#define CLK_PP_HEVC 35
|
||||
#define CLK_CLUST_HEVC 36
|
||||
#define CLK_HWPE_HEVC 37
|
||||
#define CLK_FC_HEVC 38
|
||||
#define CLK_PROC_MIXER 39
|
||||
#define CLK_PROC_SC 40
|
||||
#define CLK_AVSP_HEVC 41
|
||||
|
||||
/* CLOCKGEN D2 */
|
||||
#undef CLK_PIX_PIP
|
||||
#undef CLK_PIX_GDP1
|
||||
#undef CLK_PIX_GDP2
|
||||
#undef CLK_PIX_GDP3
|
||||
#undef CLK_PIX_GDP4
|
||||
|
||||
#define CLK_TMDS_HDMI_DIV2 5
|
||||
#define CLK_VP9 47
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user