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cmd64x: remove /proc/ide/cmd64x
This belongs to user-space (and only if really needed). text data bss dec hex filename 3874 180 28 4082 ff2 drivers/ide/pci/cmd64x.o.before 2231 180 0 2411 96b drivers/ide/pci/cmd64x.o.after Additionaly to being bloat the code reported incorrect UDMA modes for the reserved values of UDIDETCR0/1 registers. Also while at it remove unused CNTRL_DIS_RA0/1 defines. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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9e47be0c97
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/cmd64x.c Version 1.52 Dec 24, 2007
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* linux/drivers/ide/pci/cmd64x.c Version 1.53 Dec 24, 2007
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*
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* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
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* Due to massive hardware bugs, UltraDMA is only supported
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@ -22,8 +22,6 @@
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#include <asm/io.h>
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#define DISPLAY_CMD64X_TIMINGS
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#define CMD_DEBUG 0
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#if CMD_DEBUG
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@ -37,11 +35,6 @@
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*/
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#define CFR 0x50
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#define CFR_INTR_CH0 0x04
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#define CNTRL 0x51
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#define CNTRL_ENA_1ST 0x04
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#define CNTRL_ENA_2ND 0x08
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#define CNTRL_DIS_RA0 0x40
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#define CNTRL_DIS_RA1 0x80
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#define CMDTIM 0x52
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#define ARTTIM0 0x53
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@ -60,108 +53,13 @@
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define MRDMODE_BLK_CH0 0x10
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#define MRDMODE_BLK_CH1 0x20
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#define BMIDESR0 0x72
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#define UDIDETCR0 0x73
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#define DTPR0 0x74
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#define BMIDECR1 0x78
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#define BMIDECSR 0x79
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#define BMIDESR1 0x7A
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#define UDIDETCR1 0x7B
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#define DTPR1 0x7C
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#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
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#include <linux/stat.h>
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#include <linux/proc_fs.h>
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static u8 cmd64x_proc = 0;
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#define CMD_MAX_DEVS 5
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static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
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static int n_cmd_devs;
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static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
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{
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char *p = buf;
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u8 reg72 = 0, reg73 = 0; /* primary */
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u8 reg7a = 0, reg7b = 0; /* secondary */
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u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
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p += sprintf(p, "\nController: %d\n", index);
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p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
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(void) pci_read_config_byte(dev, CFR, ®50);
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(void) pci_read_config_byte(dev, CNTRL, ®51);
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(void) pci_read_config_byte(dev, ARTTIM23, ®57);
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(void) pci_read_config_byte(dev, MRDMODE, ®71);
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(void) pci_read_config_byte(dev, BMIDESR0, ®72);
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(void) pci_read_config_byte(dev, UDIDETCR0, ®73);
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(void) pci_read_config_byte(dev, BMIDESR1, ®7a);
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(void) pci_read_config_byte(dev, UDIDETCR1, ®7b);
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/* PCI0643/6 originally didn't have the primary channel enable bit */
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if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
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(dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3))
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reg51 |= CNTRL_ENA_1ST;
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p += sprintf(p, "---------------- Primary Channel "
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"---------------- Secondary Channel ------------\n");
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p += sprintf(p, " %s %s\n",
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(reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
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(reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
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p += sprintf(p, "---------------- drive0 --------- drive1 "
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"-------- drive0 --------- drive1 ------\n");
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p += sprintf(p, "DMA enabled: %s %s"
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" %s %s\n",
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(reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
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(reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
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p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
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( reg73 & 0x01) ? " on" : "off",
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((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
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((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
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((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
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((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
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( reg73 & 0x02) ? " on" : "off",
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((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
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((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
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((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
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((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
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p += sprintf(p, " %s (%c) %s (%c)\n",
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( reg7b & 0x01) ? " on" : "off",
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((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
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((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
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((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
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((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
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( reg7b & 0x02) ? " on" : "off",
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((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
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((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
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((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
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((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
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p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
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(reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
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(reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
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(reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
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(reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
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return (char *)p;
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}
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static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
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{
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char *p = buffer;
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int i;
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for (i = 0; i < n_cmd_devs; i++) {
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struct pci_dev *dev = cmd_devs[i];
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p = print_cmd64x_get_info(p, dev, i);
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}
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return p-buffer; /* => must be less than 4k! */
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}
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#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
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static u8 quantize_timing(int timing, int quant)
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{
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return (timing + quant - 1) / quant;
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@ -472,16 +370,6 @@ static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const cha
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mrdmode &= ~0x30;
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(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
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#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
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cmd_devs[n_cmd_devs++] = dev;
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if (!cmd64x_proc) {
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cmd64x_proc = 1;
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ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
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}
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#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
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return 0;
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}
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