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drm/i915: Remove distinction between DDI 2 vs 4 lanes
We never make use of the distinction between 2 vs 4 lanes so combine them into a per port domain instead. This saves us a few bits in the power domain mask. Change suggested by Ville. Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447084107-8521-7-git-send-email-patrik.jakobsson@linux.intel.com
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@ -2707,24 +2707,16 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
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return "TRANSCODER_C";
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case POWER_DOMAIN_TRANSCODER_EDP:
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return "TRANSCODER_EDP";
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case POWER_DOMAIN_PORT_DDI_A_2_LANES:
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return "PORT_DDI_A_2_LANES";
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case POWER_DOMAIN_PORT_DDI_A_4_LANES:
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return "PORT_DDI_A_4_LANES";
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case POWER_DOMAIN_PORT_DDI_B_2_LANES:
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return "PORT_DDI_B_2_LANES";
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case POWER_DOMAIN_PORT_DDI_B_4_LANES:
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return "PORT_DDI_B_4_LANES";
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case POWER_DOMAIN_PORT_DDI_C_2_LANES:
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return "PORT_DDI_C_2_LANES";
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case POWER_DOMAIN_PORT_DDI_C_4_LANES:
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return "PORT_DDI_C_4_LANES";
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case POWER_DOMAIN_PORT_DDI_D_2_LANES:
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return "PORT_DDI_D_2_LANES";
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case POWER_DOMAIN_PORT_DDI_D_4_LANES:
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return "PORT_DDI_D_4_LANES";
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case POWER_DOMAIN_PORT_DDI_E_2_LANES:
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return "PORT_DDI_E_2_LANES";
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case POWER_DOMAIN_PORT_DDI_A_LANES:
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return "PORT_DDI_A_LANES";
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case POWER_DOMAIN_PORT_DDI_B_LANES:
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return "PORT_DDI_B_LANES";
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case POWER_DOMAIN_PORT_DDI_C_LANES:
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return "PORT_DDI_C_LANES";
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case POWER_DOMAIN_PORT_DDI_D_LANES:
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return "PORT_DDI_D_LANES";
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case POWER_DOMAIN_PORT_DDI_E_LANES:
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return "PORT_DDI_E_LANES";
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case POWER_DOMAIN_PORT_DSI:
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return "PORT_DSI";
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case POWER_DOMAIN_PORT_CRT:
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@ -180,15 +180,11 @@ enum intel_display_power_domain {
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POWER_DOMAIN_TRANSCODER_B,
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POWER_DOMAIN_TRANSCODER_C,
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POWER_DOMAIN_TRANSCODER_EDP,
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POWER_DOMAIN_PORT_DDI_A_2_LANES,
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POWER_DOMAIN_PORT_DDI_A_4_LANES,
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POWER_DOMAIN_PORT_DDI_B_2_LANES,
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POWER_DOMAIN_PORT_DDI_B_4_LANES,
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POWER_DOMAIN_PORT_DDI_C_2_LANES,
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POWER_DOMAIN_PORT_DDI_C_4_LANES,
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POWER_DOMAIN_PORT_DDI_D_2_LANES,
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POWER_DOMAIN_PORT_DDI_D_4_LANES,
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POWER_DOMAIN_PORT_DDI_E_2_LANES,
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POWER_DOMAIN_PORT_DDI_A_LANES,
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POWER_DOMAIN_PORT_DDI_B_LANES,
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POWER_DOMAIN_PORT_DDI_C_LANES,
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POWER_DOMAIN_PORT_DDI_D_LANES,
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POWER_DOMAIN_PORT_DDI_E_LANES,
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POWER_DOMAIN_PORT_DSI,
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POWER_DOMAIN_PORT_CRT,
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POWER_DOMAIN_PORT_OTHER,
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@ -5141,15 +5141,15 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
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{
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switch (port) {
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case PORT_A:
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return POWER_DOMAIN_PORT_DDI_A_4_LANES;
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return POWER_DOMAIN_PORT_DDI_A_LANES;
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case PORT_B:
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return POWER_DOMAIN_PORT_DDI_B_4_LANES;
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return POWER_DOMAIN_PORT_DDI_B_LANES;
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case PORT_C:
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return POWER_DOMAIN_PORT_DDI_C_4_LANES;
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return POWER_DOMAIN_PORT_DDI_C_LANES;
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case PORT_D:
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return POWER_DOMAIN_PORT_DDI_D_4_LANES;
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return POWER_DOMAIN_PORT_DDI_D_LANES;
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case PORT_E:
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return POWER_DOMAIN_PORT_DDI_E_2_LANES;
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return POWER_DOMAIN_PORT_DDI_E_LANES;
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default:
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WARN_ON_ONCE(1);
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return POWER_DOMAIN_PORT_OTHER;
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@ -286,13 +286,10 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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BIT(POWER_DOMAIN_TRANSCODER_C) | \
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BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_AUX_D) | \
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@ -300,21 +297,17 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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BIT(POWER_DOMAIN_VGA) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
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(POWER_DOMAIN_MASK & ~( \
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@ -329,10 +322,8 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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BIT(POWER_DOMAIN_TRANSCODER_C) | \
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BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_AUDIO) | \
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@ -344,8 +335,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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BIT(POWER_DOMAIN_PIPE_A) | \
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BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
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BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
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BIT(POWER_DOMAIN_AUX_A) | \
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BIT(POWER_DOMAIN_PLLS) | \
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BIT(POWER_DOMAIN_INIT))
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@ -1421,14 +1411,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
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#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PIPE_A) | \
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BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
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BIT(POWER_DOMAIN_PORT_CRT) | \
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BIT(POWER_DOMAIN_PLLS) | \
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BIT(POWER_DOMAIN_AUX_A) | \
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@ -1452,49 +1438,42 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
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#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
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#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_PORT_CRT) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_INIT))
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#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_INIT))
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#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_INIT))
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#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_INIT))
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#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_INIT))
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#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_INIT))
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#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
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BIT(POWER_DOMAIN_AUX_D) | \
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BIT(POWER_DOMAIN_INIT))
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