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phy: meson-g12a-usb3-pcie: Add support for PCIe mode
This adds extended PCIe PHY functions for the Amlogic G12A USB3+PCIE Combo PHY to support reset, power_on and power_off for PCIe exclusively. With these callbacks, we can handle all the needed operations of the Amlogic PCIe controller driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
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@ -50,6 +50,8 @@
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#define PHY_R5_PHY_CR_ACK BIT(16)
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#define PHY_R5_PHY_CR_ACK BIT(16)
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#define PHY_R5_PHY_BS_OUT BIT(17)
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#define PHY_R5_PHY_BS_OUT BIT(17)
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#define PCIE_RESET_DELAY 500
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struct phy_g12a_usb3_pcie_priv {
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struct phy_g12a_usb3_pcie_priv {
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struct regmap *regmap;
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struct regmap *regmap;
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struct regmap *regmap_cr;
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struct regmap *regmap_cr;
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@ -196,6 +198,10 @@ static int phy_g12a_usb3_init(struct phy *phy)
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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int data, ret;
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int data, ret;
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ret = reset_control_reset(priv->reset);
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if (ret)
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return ret;
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/* Switch PHY to USB3 */
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/* Switch PHY to USB3 */
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/* TODO figure out how to handle when PCIe was set in the bootloader */
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/* TODO figure out how to handle when PCIe was set in the bootloader */
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regmap_update_bits(priv->regmap, PHY_R0,
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regmap_update_bits(priv->regmap, PHY_R0,
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@ -272,24 +278,64 @@ static int phy_g12a_usb3_init(struct phy *phy)
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return 0;
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return 0;
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}
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}
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static int phy_g12a_usb3_pcie_init(struct phy *phy)
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static int phy_g12a_usb3_pcie_power_on(struct phy *phy)
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{
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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if (priv->mode == PHY_TYPE_USB3)
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return 0;
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regmap_update_bits(priv->regmap, PHY_R0,
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PHY_R0_PCIE_POWER_STATE,
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FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
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return 0;
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}
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static int phy_g12a_usb3_pcie_power_off(struct phy *phy)
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{
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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if (priv->mode == PHY_TYPE_USB3)
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return 0;
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regmap_update_bits(priv->regmap, PHY_R0,
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PHY_R0_PCIE_POWER_STATE,
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FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
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return 0;
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}
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static int phy_g12a_usb3_pcie_reset(struct phy *phy)
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{
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{
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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int ret;
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int ret;
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ret = reset_control_reset(priv->reset);
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if (priv->mode == PHY_TYPE_USB3)
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return 0;
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ret = reset_control_assert(priv->reset);
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if (ret)
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if (ret)
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return ret;
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return ret;
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udelay(PCIE_RESET_DELAY);
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ret = reset_control_deassert(priv->reset);
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if (ret)
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return ret;
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udelay(PCIE_RESET_DELAY);
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return 0;
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}
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static int phy_g12a_usb3_pcie_init(struct phy *phy)
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{
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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if (priv->mode == PHY_TYPE_USB3)
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if (priv->mode == PHY_TYPE_USB3)
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return phy_g12a_usb3_init(phy);
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return phy_g12a_usb3_init(phy);
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/* Power UP PCIE */
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/* TODO figure out when the bootloader has set USB3 mode before */
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regmap_update_bits(priv->regmap, PHY_R0,
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PHY_R0_PCIE_POWER_STATE,
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FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
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return 0;
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return 0;
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}
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}
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@ -297,7 +343,10 @@ static int phy_g12a_usb3_pcie_exit(struct phy *phy)
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{
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{
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
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return reset_control_reset(priv->reset);
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if (priv->mode == PHY_TYPE_USB3)
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return reset_control_reset(priv->reset);
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return 0;
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}
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}
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static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
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static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
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@ -326,6 +375,9 @@ static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
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static const struct phy_ops phy_g12a_usb3_pcie_ops = {
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static const struct phy_ops phy_g12a_usb3_pcie_ops = {
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.init = phy_g12a_usb3_pcie_init,
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.init = phy_g12a_usb3_pcie_init,
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.exit = phy_g12a_usb3_pcie_exit,
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.exit = phy_g12a_usb3_pcie_exit,
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.power_on = phy_g12a_usb3_pcie_power_on,
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.power_off = phy_g12a_usb3_pcie_power_off,
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.reset = phy_g12a_usb3_pcie_reset,
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.owner = THIS_MODULE,
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.owner = THIS_MODULE,
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};
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};
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