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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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More arm64 fixes:
- Fix application of read-only permissions to kernel section mappings - Sanitise reported ESR values for signals delivered on a kernel address - Ensure tishift GCC helpers are exported to modules - Fix inline asm constraints for some LSE atomics -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJbB/1rAAoJELescNyEwWM03oIIAKVMZ6jBQFq41H+VUw7lDBMc USEzqa0hEUsaWiZW8N9penAhY2a5saYQX5srVTXy9C2JzjQ0Tc5d7BCKfc+NSjO3 OBlBNVPqwbyYwfMrNWjOVxkOHrk04gF9b6j8hwUa2g7ioWdjyP37fsh+T0pDsazM yKJt9bkjEdDDFAFqYIohEBF0LR6zXpWpCMxzZ8lcl4KcDfd85y8YBhOu211QXQoC 9PMDF9V9GzPBweAGiiET8Z0EPb5j0sCFTjNIIUiZLiP5SC7VTVJz2BqTIvolJE3o zLCPfJOCd34KbVx0S8lhPiJo652njlm2ahN5vLtVaLHQCMTAimaeYjTD7ye8jKc= =Um8e -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull more arm64 fixes from Will Deacon: - fix application of read-only permissions to kernel section mappings - sanitise reported ESR values for signals delivered on a kernel address - ensure tishift GCC helpers are exported to modules - fix inline asm constraints for some LSE atomics * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Make sure permission updates happen for pmd/pud arm64: fault: Don't leak data in ESR context for user fault on kernel VA arm64: export tishift functions to modules arm64: lse: Add early clobbers to some input/output asm operands
This commit is contained in:
Linus Torvalds
commit
62d18ecfa6
@ -117,7 +117,7 @@ static inline void atomic_and(int i, atomic_t *v)
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/* LSE atomics */
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" mvn %w[i], %w[i]\n"
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" stclr %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: [i] "+&r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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@ -135,7 +135,7 @@ static inline int atomic_fetch_and##name(int i, atomic_t *v) \
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/* LSE atomics */ \
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" mvn %w[i], %w[i]\n" \
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" ldclr" #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: [i] "+&r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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@ -161,7 +161,7 @@ static inline void atomic_sub(int i, atomic_t *v)
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/* LSE atomics */
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" neg %w[i], %w[i]\n"
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" stadd %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: [i] "+&r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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@ -180,7 +180,7 @@ static inline int atomic_sub_return##name(int i, atomic_t *v) \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], w30, %[v]\n" \
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" add %w[i], %w[i], w30") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: [i] "+&r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS , ##cl); \
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\
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@ -207,7 +207,7 @@ static inline int atomic_fetch_sub##name(int i, atomic_t *v) \
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/* LSE atomics */ \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: [i] "+&r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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@ -314,7 +314,7 @@ static inline void atomic64_and(long i, atomic64_t *v)
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/* LSE atomics */
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" mvn %[i], %[i]\n"
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" stclr %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: [i] "+&r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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@ -332,7 +332,7 @@ static inline long atomic64_fetch_and##name(long i, atomic64_t *v) \
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/* LSE atomics */ \
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" mvn %[i], %[i]\n" \
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" ldclr" #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: [i] "+&r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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@ -358,7 +358,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
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/* LSE atomics */
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" neg %[i], %[i]\n"
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" stadd %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: [i] "+&r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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@ -377,7 +377,7 @@ static inline long atomic64_sub_return##name(long i, atomic64_t *v) \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], x30, %[v]\n" \
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" add %[i], %[i], x30") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: [i] "+&r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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@ -404,7 +404,7 @@ static inline long atomic64_fetch_sub##name(long i, atomic64_t *v) \
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/* LSE atomics */ \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: [i] "+&r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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@ -435,7 +435,7 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
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" sub x30, x30, %[ret]\n"
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" cbnz x30, 1b\n"
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"2:")
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: [ret] "+r" (x0), [v] "+Q" (v->counter)
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: [ret] "+&r" (x0), [v] "+Q" (v->counter)
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:
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: __LL_SC_CLOBBERS, "cc", "memory");
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@ -516,7 +516,7 @@ static inline long __cmpxchg_double##name(unsigned long old1, \
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" eor %[old1], %[old1], %[oldval1]\n" \
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" eor %[old2], %[old2], %[oldval2]\n" \
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" orr %[old1], %[old1], %[old2]") \
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: [old1] "+r" (x0), [old2] "+r" (x1), \
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: [old1] "+&r" (x0), [old2] "+&r" (x1), \
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[v] "+Q" (*(unsigned long *)ptr) \
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: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
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[oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
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@ -75,3 +75,11 @@ NOKPROBE_SYMBOL(_mcount);
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/* arm-smccc */
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EXPORT_SYMBOL(__arm_smccc_smc);
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EXPORT_SYMBOL(__arm_smccc_hvc);
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/* tishift.S */
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extern long long __ashlti3(long long a, int b);
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EXPORT_SYMBOL(__ashlti3);
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extern long long __ashrti3(long long a, int b);
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EXPORT_SYMBOL(__ashrti3);
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extern long long __lshrti3(long long a, int b);
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EXPORT_SYMBOL(__lshrti3);
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@ -1,17 +1,6 @@
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/*
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* Copyright (C) 2017 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* Copyright (C) 2017-2018 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
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*/
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#include <linux/linkage.h>
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@ -293,6 +293,57 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr,
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static void __do_user_fault(struct siginfo *info, unsigned int esr)
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{
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current->thread.fault_address = (unsigned long)info->si_addr;
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/*
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* If the faulting address is in the kernel, we must sanitize the ESR.
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* From userspace's point of view, kernel-only mappings don't exist
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* at all, so we report them as level 0 translation faults.
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* (This is not quite the way that "no mapping there at all" behaves:
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* an alignment fault not caused by the memory type would take
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* precedence over translation fault for a real access to empty
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* space. Unfortunately we can't easily distinguish "alignment fault
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* not caused by memory type" from "alignment fault caused by memory
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* type", so we ignore this wrinkle and just return the translation
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* fault.)
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*/
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if (current->thread.fault_address >= TASK_SIZE) {
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switch (ESR_ELx_EC(esr)) {
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case ESR_ELx_EC_DABT_LOW:
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/*
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* These bits provide only information about the
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* faulting instruction, which userspace knows already.
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* We explicitly clear bits which are architecturally
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* RES0 in case they are given meanings in future.
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* We always report the ESR as if the fault was taken
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* to EL1 and so ISV and the bits in ISS[23:14] are
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* clear. (In fact it always will be a fault to EL1.)
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*/
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esr &= ESR_ELx_EC_MASK | ESR_ELx_IL |
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ESR_ELx_CM | ESR_ELx_WNR;
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esr |= ESR_ELx_FSC_FAULT;
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break;
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case ESR_ELx_EC_IABT_LOW:
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/*
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* Claim a level 0 translation fault.
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* All other bits are architecturally RES0 for faults
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* reported with that DFSC value, so we clear them.
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*/
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esr &= ESR_ELx_EC_MASK | ESR_ELx_IL;
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esr |= ESR_ELx_FSC_FAULT;
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break;
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default:
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/*
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* This should never happen (entry.S only brings us
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* into this code for insn and data aborts from a lower
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* exception level). Fail safe by not providing an ESR
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* context record at all.
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*/
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WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr);
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esr = 0;
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break;
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}
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}
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current->thread.fault_code = esr;
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arm64_force_sig_info(info, esr_to_fault_info(esr)->name, current);
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}
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@ -933,13 +933,15 @@ int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot)
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{
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pgprot_t sect_prot = __pgprot(PUD_TYPE_SECT |
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pgprot_val(mk_sect_prot(prot)));
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pud_t new_pud = pfn_pud(__phys_to_pfn(phys), sect_prot);
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/* ioremap_page_range doesn't honour BBM */
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if (pud_present(READ_ONCE(*pudp)))
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/* Only allow permission changes for now */
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if (!pgattr_change_is_safe(READ_ONCE(pud_val(*pudp)),
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pud_val(new_pud)))
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return 0;
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BUG_ON(phys & ~PUD_MASK);
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set_pud(pudp, pfn_pud(__phys_to_pfn(phys), sect_prot));
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set_pud(pudp, new_pud);
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return 1;
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}
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@ -947,13 +949,15 @@ int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot)
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{
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pgprot_t sect_prot = __pgprot(PMD_TYPE_SECT |
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pgprot_val(mk_sect_prot(prot)));
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pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), sect_prot);
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/* ioremap_page_range doesn't honour BBM */
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if (pmd_present(READ_ONCE(*pmdp)))
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/* Only allow permission changes for now */
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if (!pgattr_change_is_safe(READ_ONCE(pmd_val(*pmdp)),
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pmd_val(new_pmd)))
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return 0;
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BUG_ON(phys & ~PMD_MASK);
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set_pmd(pmdp, pfn_pmd(__phys_to_pfn(phys), sect_prot));
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set_pmd(pmdp, new_pmd);
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return 1;
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}
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