mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/display: Rename DCN TG specific function prefixes to tg
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
Alex Deucher
parent
c3aa1d6729
commit
62a3213aca
@ -44,7 +44,7 @@
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* This is a workaround for a bug that has existed since R5xx and has not been
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* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
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*/
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static void tg_apply_front_porch_workaround(
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static void tgn10_apply_front_porch_workaround(
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struct timing_generator *tg,
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struct dc_crtc_timing *timing)
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{
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@ -57,7 +57,7 @@ static void tg_apply_front_porch_workaround(
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}
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}
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static void dcn10_program_global_sync(
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static void tgn10_program_global_sync(
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struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -78,7 +78,7 @@ static void dcn10_program_global_sync(
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VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
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}
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static void dcn10_disable_stereo(struct timing_generator *tg)
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static void tgn10_disable_stereo(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -101,9 +101,10 @@ static void dcn10_disable_stereo(struct timing_generator *tg)
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* Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
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* Including SYNC. Call BIOS command table to program Timings.
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*/
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static void tg_program_timing_generator(
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static void tgn10_program_timing(
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struct timing_generator *tg,
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const struct dc_crtc_timing *dc_crtc_timing)
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const struct dc_crtc_timing *dc_crtc_timing,
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bool use_vbios)
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{
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struct dc_crtc_timing patched_crtc_timing;
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uint32_t vesa_sync_start;
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@ -118,11 +119,10 @@ static void tg_program_timing_generator(
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uint32_t field_num = 0;
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uint32_t h_div_2;
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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patched_crtc_timing = *dc_crtc_timing;
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tg_apply_front_porch_workaround(tg, &patched_crtc_timing);
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tgn10_apply_front_porch_workaround(tg, &patched_crtc_timing);
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/* Load horizontal timing */
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@ -253,7 +253,7 @@ static void tg_program_timing_generator(
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OTG_START_POINT_CNTL, start_point,
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OTG_FIELD_NUMBER_CNTL, field_num);
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dcn10_program_global_sync(tg);
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tgn10_program_global_sync(tg);
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/* TODO
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* patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
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@ -273,25 +273,11 @@ static void tg_program_timing_generator(
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}
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/** tg_program_blanking
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* Only programmed part of OTG_H, OTG_V register for set_plane_config
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* Assume other OTG registers are programmed by video mode set already.
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* This function is for underlay. DCN will have new sequence.
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* This function will be removed. Need remove it from set_plane_config
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*/
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static void tg_program_timing(struct timing_generator *tg,
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const struct dc_crtc_timing *timing,
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bool use_vbios)
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{
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tg_program_timing_generator(tg, timing);
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}
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/**
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* unblank_crtc
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* Call ASIC Control Object to UnBlank CRTC.
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*/
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static void tg_unblank_crtc(struct timing_generator *tg)
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static void tgn10_unblank_crtc(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -305,7 +291,7 @@ static void tg_unblank_crtc(struct timing_generator *tg)
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* Call ASIC Control Object to Blank CRTC.
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*/
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static void tg_blank_crtc(struct timing_generator *tg)
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static void tgn10_blank_crtc(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -324,16 +310,16 @@ static void tg_blank_crtc(struct timing_generator *tg)
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OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
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}
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static void tg_set_blank(struct timing_generator *tg,
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static void tgn10_set_blank(struct timing_generator *tg,
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bool enable_blanking)
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{
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if (enable_blanking)
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tg_blank_crtc(tg);
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tgn10_blank_crtc(tg);
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else
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tg_unblank_crtc(tg);
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tgn10_unblank_crtc(tg);
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}
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static bool tg_is_blanked(struct timing_generator *tg)
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static bool tgn10_is_blanked(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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uint32_t blank_en;
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@ -346,7 +332,7 @@ static bool tg_is_blanked(struct timing_generator *tg)
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return blank_en && blank_state;
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}
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static void enable_optc_clock(struct timing_generator *tg, bool enable)
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static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -388,7 +374,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable)
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* Enable CRTC
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* Enable CRTC - call ASIC Control Object to enable Timing generator.
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*/
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static bool tg_enable_crtc(struct timing_generator *tg)
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static bool tgn10_enable_crtc(struct timing_generator *tg)
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{
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/* TODO FPGA wait for answer
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* OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
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@ -415,7 +401,7 @@ static bool tg_enable_crtc(struct timing_generator *tg)
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}
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/* disable_crtc - call ASIC Control Object to disable Timing generator. */
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static bool tg_disable_crtc(struct timing_generator *tg)
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static bool tgn10_disable_crtc(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -438,7 +424,7 @@ static bool tg_disable_crtc(struct timing_generator *tg)
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}
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static void tg_program_blank_color(
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static void tgn10_program_blank_color(
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struct timing_generator *tg,
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const struct tg_color *black_color)
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{
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@ -464,7 +450,7 @@ static void tg_program_blank_color(
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* We may move init_hw into DC specific so that we can remove
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* .disable_vga from upper layer stack
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*/
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static void dcn10_timing_generator_disable_vga(
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static void tgn10_disable_vga(
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struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -487,7 +473,7 @@ static void dcn10_timing_generator_disable_vga(
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}
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}
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static bool tg_validate_timing(
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static bool tgn10_validate_timing(
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struct timing_generator *tg,
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const struct dc_crtc_timing *timing)
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{
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@ -560,7 +546,7 @@ static bool tg_validate_timing(
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* @return
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* Counter of frames, which should equal to number of vblanks.
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*/
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static uint32_t tg_get_vblank_counter(struct timing_generator *tg)
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static uint32_t tgn10_get_vblank_counter(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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uint32_t frame_count;
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@ -571,7 +557,7 @@ static uint32_t tg_get_vblank_counter(struct timing_generator *tg)
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return frame_count;
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}
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void dcn10_lock(struct timing_generator *tg)
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static void tgn10_lock(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -581,7 +567,7 @@ void dcn10_lock(struct timing_generator *tg)
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OTG_MASTER_UPDATE_LOCK, 1);
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}
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void dcn10_unlock(struct timing_generator *tg)
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static void tgn10_unlock(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -594,7 +580,7 @@ void dcn10_unlock(struct timing_generator *tg)
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20000, 200000);*/
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}
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static void dcn10_get_position(struct timing_generator *tg,
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static void tgn10_get_position(struct timing_generator *tg,
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struct crtc_position *position)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -607,7 +593,7 @@ static void dcn10_get_position(struct timing_generator *tg,
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OTG_VERT_COUNT_NOM, &position->nominal_vcount);
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}
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bool dcn10_is_counter_moving(struct timing_generator *tg)
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static bool tgn10_is_counter_moving(struct timing_generator *tg)
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{
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struct crtc_position position1, position2;
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@ -621,7 +607,7 @@ bool dcn10_is_counter_moving(struct timing_generator *tg)
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return true;
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}
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static bool dcn10_did_triggered_reset_occur(
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static bool tgn10_did_triggered_reset_occur(
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struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -633,7 +619,7 @@ static bool dcn10_did_triggered_reset_occur(
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return occurred != 0;
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}
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static void dcn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst)
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static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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uint32_t falling_edge;
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@ -667,7 +653,7 @@ static void dcn10_enable_reset_trigger(struct timing_generator *tg, int source_t
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OTG_FORCE_COUNT_NOW_MODE, 2);
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}
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static void dcn10_disable_reset_trigger(struct timing_generator *tg)
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static void tgn10_disable_reset_trigger(struct timing_generator *tg)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -677,7 +663,7 @@ static void dcn10_disable_reset_trigger(struct timing_generator *tg)
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OTG_FORCE_COUNT_NOW_CLEAR, 1);
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}
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static void dcn10_wait_for_state(struct timing_generator *tg,
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static void tgn10_wait_for_state(struct timing_generator *tg,
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enum crtc_state state)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -700,7 +686,7 @@ static void dcn10_wait_for_state(struct timing_generator *tg,
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}
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}
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static void set_early_control(
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static void tgn10_set_early_control(
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struct timing_generator *tg,
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uint32_t early_cntl)
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{
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@ -710,7 +696,7 @@ static void set_early_control(
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}
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static void set_static_screen_control(
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static void tgn10_set_static_screen_control(
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struct timing_generator *tg,
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uint32_t value)
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{
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@ -739,7 +725,7 @@ static void set_static_screen_control(
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*
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*****************************************************************************
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*/
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void dcn10_timing_generator_set_drr(
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static void tgn10_set_drr(
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struct timing_generator *tg,
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const struct drr_params *params)
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{
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@ -776,7 +762,7 @@ void dcn10_timing_generator_set_drr(
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}
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}
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static void dcn10_timing_generator_set_test_pattern(
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static void tgn10_set_test_pattern(
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struct timing_generator *tg,
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/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
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* because this is not DP-specific (which is probably somewhere in DP
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@ -1035,7 +1021,7 @@ static void dcn10_timing_generator_set_test_pattern(
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}
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}
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void dcn10_timing_generator_get_crtc_scanoutpos(
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static void tgn10_get_crtc_scanoutpos(
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struct timing_generator *tg,
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uint32_t *v_blank_start,
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uint32_t *v_blank_end,
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@ -1049,7 +1035,7 @@ void dcn10_timing_generator_get_crtc_scanoutpos(
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OTG_V_BLANK_START, v_blank_start,
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OTG_V_BLANK_END, v_blank_end);
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dcn10_get_position(tg, &position);
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tgn10_get_position(tg, &position);
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*h_position = position.horizontal_count;
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*v_position = position.vertical_count;
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@ -1057,7 +1043,7 @@ void dcn10_timing_generator_get_crtc_scanoutpos(
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static void dcn10_enable_stereo(struct timing_generator *tg,
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static void tgn10_enable_stereo(struct timing_generator *tg,
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const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
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{
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struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
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@ -1099,17 +1085,17 @@ static void dcn10_enable_stereo(struct timing_generator *tg,
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OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
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}
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static void dcn10_program_stereo(struct timing_generator *tg,
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static void tgn10_program_stereo(struct timing_generator *tg,
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const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
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{
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if (flags->PROGRAM_STEREO)
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dcn10_enable_stereo(tg, timing, flags);
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tgn10_enable_stereo(tg, timing, flags);
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else
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dcn10_disable_stereo(tg);
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tgn10_disable_stereo(tg);
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}
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static bool dcn10_is_stereo_left_eye(struct timing_generator *tg)
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static bool tgn10_is_stereo_left_eye(struct timing_generator *tg)
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{
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bool ret = false;
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uint32_t left_eye = 0;
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@ -1126,46 +1112,34 @@ static bool dcn10_is_stereo_left_eye(struct timing_generator *tg)
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}
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static struct timing_generator_funcs dcn10_tg_funcs = {
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.validate_timing = tg_validate_timing,
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.program_timing = tg_program_timing,
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.program_global_sync = dcn10_program_global_sync,
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.enable_crtc = tg_enable_crtc,
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.disable_crtc = tg_disable_crtc,
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.validate_timing = tgn10_validate_timing,
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.program_timing = tgn10_program_timing,
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.program_global_sync = tgn10_program_global_sync,
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.enable_crtc = tgn10_enable_crtc,
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.disable_crtc = tgn10_disable_crtc,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.is_counter_moving = dcn10_is_counter_moving,
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/* never be called */
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.get_position = dcn10_get_position,
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.get_frame_count = tg_get_vblank_counter,
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.get_scanoutpos = dcn10_timing_generator_get_crtc_scanoutpos,
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.set_early_control = set_early_control,
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.is_counter_moving = tgn10_is_counter_moving,
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.get_position = tgn10_get_position,
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.get_frame_count = tgn10_get_vblank_counter,
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.get_scanoutpos = tgn10_get_crtc_scanoutpos,
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.set_early_control = tgn10_set_early_control,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.wait_for_state = dcn10_wait_for_state,
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.set_blank = tg_set_blank,
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.is_blanked = tg_is_blanked,
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/* never be called */
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.set_colors = NULL,
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/* this function will be called by .progam_scaler. dcn and dce
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* scaler top level functions are different. .program_scaler is
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* not need for dcn. within program_scaler, dcn will return
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* early before set_overscan_blank_color is reached
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*/
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.set_overscan_blank_color = NULL,
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.set_blank_color = tg_program_blank_color,
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/* dcn10_timing_generator_disable_vga */
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.disable_vga = dcn10_timing_generator_disable_vga,
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.did_triggered_reset_occur = dcn10_did_triggered_reset_occur,
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.enable_reset_trigger = dcn10_enable_reset_trigger,
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.disable_reset_trigger = dcn10_disable_reset_trigger,
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.lock = dcn10_lock,
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.unlock = dcn10_unlock,
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/* dcn10_timing_generator_enable_advanced_request*/
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.enable_advanced_request = NULL,
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.enable_optc_clock = enable_optc_clock,
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.set_drr = dcn10_timing_generator_set_drr,
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.set_static_screen_control = set_static_screen_control,
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.set_test_pattern = dcn10_timing_generator_set_test_pattern,
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.program_stereo = dcn10_program_stereo,
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.is_stereo_left_eye = dcn10_is_stereo_left_eye
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.wait_for_state = tgn10_wait_for_state,
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.set_blank = tgn10_set_blank,
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.is_blanked = tgn10_is_blanked,
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.set_blank_color = tgn10_program_blank_color,
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.disable_vga = tgn10_disable_vga,
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.did_triggered_reset_occur = tgn10_did_triggered_reset_occur,
|
||||
.enable_reset_trigger = tgn10_enable_reset_trigger,
|
||||
.disable_reset_trigger = tgn10_disable_reset_trigger,
|
||||
.lock = tgn10_lock,
|
||||
.unlock = tgn10_unlock,
|
||||
.enable_optc_clock = tgn10_enable_optc_clock,
|
||||
.set_drr = tgn10_set_drr,
|
||||
.set_static_screen_control = tgn10_set_static_screen_control,
|
||||
.set_test_pattern = tgn10_set_test_pattern,
|
||||
.program_stereo = tgn10_program_stereo,
|
||||
.is_stereo_left_eye = tgn10_is_stereo_left_eye
|
||||
};
|
||||
|
||||
void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
|
||||
@ -1181,4 +1155,3 @@ void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
|
||||
tgn10->min_h_sync_width = 8;
|
||||
tgn10->min_v_sync_width = 1;
|
||||
}
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
#define DCN10TG_FROM_TG(tg)\
|
||||
container_of(tg, struct dcn10_timing_generator, base)
|
||||
|
||||
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
|
||||
#define TG_COMMON_REG_LIST_DCN(inst) \
|
||||
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
|
||||
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
|
||||
SRI(OTG_VREADY_PARAM, OTG, inst),\
|
||||
@ -64,9 +64,6 @@
|
||||
SRI(OTG_STATUS_POSITION, OTG, inst),\
|
||||
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
|
||||
SRI(OTG_BLACK_COLOR, OTG, inst),\
|
||||
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
|
||||
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
|
||||
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
|
||||
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
|
||||
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
|
||||
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
|
||||
@ -76,7 +73,14 @@
|
||||
SR(D1VGA_CONTROL),\
|
||||
SR(D2VGA_CONTROL),\
|
||||
SR(D3VGA_CONTROL),\
|
||||
SR(D4VGA_CONTROL),\
|
||||
SR(D4VGA_CONTROL)
|
||||
|
||||
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
|
||||
TG_COMMON_REG_LIST_DCN(inst),\
|
||||
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
|
||||
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
|
||||
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
|
||||
|
||||
|
||||
struct dcn_tg_registers {
|
||||
uint32_t OTG_VSTARTUP_PARAM;
|
||||
@ -127,7 +131,7 @@ struct dcn_tg_registers {
|
||||
uint32_t D4VGA_CONTROL;
|
||||
};
|
||||
|
||||
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
|
||||
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
|
||||
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
|
||||
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
|
||||
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
|
||||
@ -192,6 +196,21 @@ struct dcn_tg_registers {
|
||||
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
|
||||
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
|
||||
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
|
||||
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
|
||||
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
|
||||
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
|
||||
SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
|
||||
SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
|
||||
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
|
||||
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
|
||||
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh)
|
||||
|
||||
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
|
||||
TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
|
||||
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
|
||||
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
|
||||
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
|
||||
@ -203,19 +222,7 @@ struct dcn_tg_registers {
|
||||
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
|
||||
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
|
||||
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
|
||||
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
|
||||
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
|
||||
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
|
||||
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
|
||||
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
|
||||
SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
|
||||
SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
|
||||
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
|
||||
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
|
||||
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
|
||||
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh)
|
||||
|
||||
#define TG_REG_FIELD_LIST(type) \
|
||||
type VSTARTUP_START;\
|
||||
@ -300,11 +307,12 @@ struct dcn_tg_registers {
|
||||
type OPTC_INPUT_CLK_ON;\
|
||||
type OPTC_INPUT_CLK_GATE_DIS;\
|
||||
type OPTC_SRC_SEL;\
|
||||
type OPTC_SEG0_SRC_SEL;\
|
||||
type OPPBUF_ACTIVE_WIDTH;\
|
||||
type OPPBUF_3D_VACT_SPACE1_SIZE;\
|
||||
type VTG0_ENABLE;\
|
||||
type VTG0_FP2;\
|
||||
type VTG0_VCOUNT_INIT;\
|
||||
type VTG0_VCOUNT_INIT;
|
||||
|
||||
struct dcn_tg_shift {
|
||||
TG_REG_FIELD_LIST(uint8_t)
|
||||
@ -336,9 +344,4 @@ struct dcn10_timing_generator {
|
||||
|
||||
void dcn10_timing_generator_init(struct dcn10_timing_generator *tg);
|
||||
|
||||
void dcn10_timing_generator_set_drr(struct timing_generator *tg,
|
||||
const struct drr_params *params);
|
||||
|
||||
void dcn10_unlock(struct timing_generator *tg);
|
||||
void dcn10_lock(struct timing_generator *tg);
|
||||
#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user