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clk: renesas: Updates for v4.8 (take two)

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- Add support for R-Car V2H,
   - Add FDP1, DRIF, and thermal clocks on R-Car H3,
   - Correct a wrong parent clock.
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Merge tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull second batch of Renesas clk driver updates from Geert
Uytterhoeven:

  - Add support for R-Car V2H,
  - Add FDP1, DRIF, and thermal clocks on R-Car H3,
  - Correct a wrong parent clock.

* tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7795: Add THS/TSC clock
  clk: renesas: r8a7795: Add DRIF clock
  clk: renesas: r8a7795: Correct lvds clock parent
  clk: renesas: r8a7795: Provide FDP1 clocks
  clk: renesas: Add R8A7792 support
  clk: renesas: mstp: Document R8A7792 support
  clk: renesas: rcar-gen2: Document R8A7792 support
This commit is contained in:
Stephen Boyd 2016-06-29 10:53:31 -07:00
commit 629ff48669
5 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
View File

@ -17,6 +17,7 @@ Required Properties:
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks

1
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- compatible: Must be one of
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
and "renesas,rcar-gen2-cpg-clocks" as a fallback.

1
drivers/clk/renesas/Kconfig
View File

@ -12,6 +12,7 @@ config CLK_RENESAS_CPG_MSTP
default y if ARCH_R8A7779
default y if ARCH_R8A7790
default y if ARCH_R8A7791
default y if ARCH_R8A7792
default y if ARCH_R8A7793
default y if ARCH_R8A7794
default y if ARCH_SH73A0

1
drivers/clk/renesas/Makefile
View File

@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7792) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o

14
drivers/clk/renesas/r8a7795-cpg-mssr.c
View File

@ -107,6 +107,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1),
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S2D1),
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S2D1),
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
@ -135,11 +138,20 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
@ -177,7 +189,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
DEF_MOD("lvds", 727, R8A7795_CLK_S2D1),
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
DEF_MOD("vin7", 804, R8A7795_CLK_S2D1),