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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 00:16:44 +07:00
intel-gtt: switch i81x to the write_entry helpers
Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Daniel Vetter
Chris Wilson
parent
24a6b387af
commit
625dd9d331
@ -101,6 +101,9 @@ static struct _intel_private {
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dma_addr_t scratch_page_dma;
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} intel_private;
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static int intel_fake_agp_insert_entries(struct agp_memory *mem,
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off_t pg_start, int type);
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#define INTEL_GTT_GEN intel_private.driver->gen
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#define IS_G33 intel_private.driver->is_g33
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#define IS_PINEVIEW intel_private.driver->is_pineview
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@ -176,10 +179,12 @@ static int intel_i810_fetch_size(void)
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if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
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agp_bridge->current_size = (void *) (values + 1);
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agp_bridge->aperture_size_idx = 1;
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intel_private.base.gtt_total_entries = KB(32) / 4;
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return values[1].size;
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} else {
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agp_bridge->current_size = (void *) (values);
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agp_bridge->aperture_size_idx = 0;
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intel_private.base.gtt_total_entries = KB(64) / 4;
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return values[0].size;
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}
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@ -206,6 +211,9 @@ static int intel_i810_configure(void)
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}
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}
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intel_private.gtt = intel_private.registers + I810_PTE_BASE;
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intel_private.scratch_page_dma = agp_bridge->scratch_page & PAGE_MASK;
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if ((readl(intel_private.registers+I810_DRAM_CTL)
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& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
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/* This will need to be dynamically assigned */
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@ -272,80 +280,28 @@ static void i8xx_destroy_pages(struct page *page)
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static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int i, j, num_entries;
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void *temp;
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int ret = -EINVAL;
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int mask_type;
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if (mem->page_count == 0)
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goto out;
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temp = agp_bridge->current_size;
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num_entries = A_SIZE_FIX(temp)->num_entries;
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if ((pg_start + mem->page_count) > num_entries)
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goto out_err;
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for (j = pg_start; j < (pg_start + mem->page_count); j++) {
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if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
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ret = -EBUSY;
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goto out_err;
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}
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}
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if (type != mem->type)
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goto out_err;
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mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
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switch (mask_type) {
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case AGP_DCACHE_MEMORY:
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if (!mem->is_flushed)
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global_cache_flush();
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for (i = pg_start; i < (pg_start + mem->page_count); i++) {
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writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
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intel_private.registers+I810_PTE_BASE+(i*4));
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}
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readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
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break;
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case AGP_PHYS_MEMORY:
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case AGP_NORMAL_MEMORY:
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if (!mem->is_flushed)
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global_cache_flush();
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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page_to_phys(mem->pages[i]), mask_type),
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intel_private.registers+I810_PTE_BASE+(j*4));
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}
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readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
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break;
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default:
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goto out_err;
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}
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out:
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ret = 0;
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out_err:
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mem->is_flushed = true;
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return ret;
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}
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static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int i;
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if (mem->page_count == 0)
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if (type == AGP_DCACHE_MEMORY) {
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if ((pg_start + mem->page_count)
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> intel_private.num_dcache_entries)
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return -EINVAL;
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if (!mem->is_flushed)
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global_cache_flush();
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for (i = pg_start; i < (pg_start + mem->page_count); i++) {
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dma_addr_t addr = i << PAGE_SHIFT;
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intel_private.driver->write_entry(addr,
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i, type);
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}
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readl(intel_private.gtt+i-1);
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return 0;
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
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}
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readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
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return 0;
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return intel_fake_agp_insert_entries(mem, pg_start, type);
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}
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/*
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@ -390,29 +346,6 @@ static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
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return new;
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}
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static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
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{
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struct agp_memory *new;
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if (type == AGP_DCACHE_MEMORY) {
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if (pg_count != intel_private.num_dcache_entries)
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return NULL;
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new = agp_create_memory(1);
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if (new == NULL)
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return NULL;
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new->type = AGP_DCACHE_MEMORY;
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new->page_count = pg_count;
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new->num_scratch_pages = 0;
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agp_free_page_array(new);
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return new;
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}
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if (type == AGP_PHYS_MEMORY)
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return alloc_agpphysmem_i8xx(pg_count, type);
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return NULL;
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}
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static void intel_i810_free_by_type(struct agp_memory *curr)
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{
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agp_free_key(curr->key);
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@ -463,6 +396,23 @@ static int intel_gtt_setup_scratch_page(void)
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return 0;
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}
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static void i810_write_entry(dma_addr_t addr, unsigned int entry,
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unsigned int flags)
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{
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u32 pte_flags = I810_PTE_VALID;
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switch (flags) {
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case AGP_DCACHE_MEMORY:
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pte_flags |= I810_PTE_LOCAL;
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break;
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case AGP_USER_CACHED_MEMORY:
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pte_flags |= I830_PTE_SYSTEM_CACHED;
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break;
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}
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writel(addr | pte_flags, intel_private.gtt + entry);
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}
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static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
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{128, 32768, 5},
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/* The 64M mode still requires a 128k gatt */
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@ -760,7 +710,7 @@ static void intel_gtt_cleanup(void)
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iounmap(intel_private.gtt);
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iounmap(intel_private.registers);
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intel_gtt_teardown_scratch_page();
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}
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@ -889,7 +839,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,
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unsigned int flags)
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{
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u32 pte_flags = I810_PTE_VALID;
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if (flags == AGP_USER_CACHED_MEMORY)
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pte_flags |= I830_PTE_SYSTEM_CACHED;
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@ -1106,6 +1056,22 @@ static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge)
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static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
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int type)
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{
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struct agp_memory *new;
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if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
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if (pg_count != intel_private.num_dcache_entries)
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return NULL;
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new = agp_create_memory(1);
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if (new == NULL)
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return NULL;
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new->type = AGP_DCACHE_MEMORY;
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new->page_count = pg_count;
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new->num_scratch_pages = 0;
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agp_free_page_array(new);
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return new;
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}
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if (type == AGP_PHYS_MEMORY)
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return alloc_agpphysmem_i8xx(pg_count, type);
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/* always return NULL for other allocation types for now */
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@ -1316,8 +1282,8 @@ static const struct agp_bridge_driver intel_810_driver = {
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = intel_i810_insert_entries,
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.remove_memory = intel_i810_remove_entries,
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.alloc_by_type = intel_i810_alloc_by_type,
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.remove_memory = intel_fake_agp_remove_entries,
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.alloc_by_type = intel_fake_agp_alloc_by_type,
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.free_by_type = intel_i810_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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@ -1352,6 +1318,8 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
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static const struct intel_gtt_driver i81x_gtt_driver = {
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.gen = 1,
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.dma_mask_size = 32,
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.check_flags = i830_check_flags,
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.write_entry = i810_write_entry,
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};
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static const struct intel_gtt_driver i8xx_gtt_driver = {
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.gen = 2,
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@ -1369,7 +1337,7 @@ static const struct intel_gtt_driver i915_gtt_driver = {
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.setup = i9xx_setup,
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.cleanup = i9xx_cleanup,
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/* i945 is the last gpu to need phys mem (for overlay and cursors). */
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.write_entry = i830_write_entry,
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.write_entry = i830_write_entry,
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.dma_mask_size = 32,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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@ -1557,7 +1525,7 @@ int intel_gmch_probe(struct pci_dev *pdev,
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if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
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bridge->driver =
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intel_gtt_chipsets[i].gmch_driver;
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intel_private.driver =
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intel_private.driver =
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intel_gtt_chipsets[i].gtt_driver;
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break;
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}
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