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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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tty: serial: fsl_lpuart: Use scatter/gather DMA for Tx
Drop PIO to DMA switching and use scatter/gather DMA for Tx path to improve performance. Some part of the code is borrowed from imx serial driver. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Bhuvanchandra DV
Greg Kroah-Hartman
parent
5887ad43ee
commit
6250cc30c4
@ -244,18 +244,18 @@ struct lpuart_port {
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struct dma_chan *dma_rx_chan;
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struct dma_async_tx_descriptor *dma_tx_desc;
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struct dma_async_tx_descriptor *dma_rx_desc;
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dma_addr_t dma_tx_buf_bus;
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dma_cookie_t dma_tx_cookie;
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dma_cookie_t dma_rx_cookie;
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unsigned char *dma_tx_buf_virt;
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unsigned int dma_tx_bytes;
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unsigned int dma_rx_bytes;
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int dma_tx_in_progress;
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bool dma_tx_in_progress;
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unsigned int dma_rx_timeout;
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struct timer_list lpuart_timer;
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struct scatterlist rx_sgl;
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struct scatterlist rx_sgl, tx_sgl[2];
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struct circ_buf rx_ring;
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int rx_dma_rng_buf_len;
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unsigned int dma_tx_nents;
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wait_queue_head_t dma_wait;
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};
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static const struct of_device_id lpuart_dt_ids[] = {
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@ -316,103 +316,118 @@ static void lpuart32_stop_rx(struct uart_port *port)
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lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
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}
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static void lpuart_pio_tx(struct lpuart_port *sport)
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static void lpuart_dma_tx(struct lpuart_port *sport)
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{
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struct circ_buf *xmit = &sport->port.state->xmit;
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unsigned long flags;
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struct scatterlist *sgl = sport->tx_sgl;
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struct device *dev = sport->port.dev;
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int ret;
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spin_lock_irqsave(&sport->port.lock, flags);
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if (sport->dma_tx_in_progress)
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return;
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while (!uart_circ_empty(xmit) &&
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readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
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writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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sport->port.icount.tx++;
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sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
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if (xmit->tail < xmit->head) {
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sport->dma_tx_nents = 1;
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sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
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} else {
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sport->dma_tx_nents = 2;
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sg_init_table(sgl, 2);
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sg_set_buf(sgl, xmit->buf + xmit->tail,
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UART_XMIT_SIZE - xmit->tail);
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sg_set_buf(sgl + 1, xmit->buf, xmit->head);
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&sport->port);
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ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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if (!ret) {
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dev_err(dev, "DMA mapping error for TX.\n");
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return;
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}
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if (uart_circ_empty(xmit))
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writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
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sport->port.membase + UARTCR5);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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}
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static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
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{
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struct circ_buf *xmit = &sport->port.state->xmit;
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dma_addr_t tx_bus_addr;
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dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
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tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
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sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
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tx_bus_addr, sport->dma_tx_bytes,
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sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
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sport->dma_tx_nents,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
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if (!sport->dma_tx_desc) {
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dev_err(sport->port.dev, "Not able to get desc for tx\n");
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return -EIO;
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dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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dev_err(dev, "Cannot prepare TX slave DMA!\n");
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return;
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}
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sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
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sport->dma_tx_desc->callback_param = sport;
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sport->dma_tx_in_progress = 1;
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sport->dma_tx_in_progress = true;
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sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
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dma_async_issue_pending(sport->dma_tx_chan);
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return 0;
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}
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static void lpuart_prepare_tx(struct lpuart_port *sport)
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{
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struct circ_buf *xmit = &sport->port.state->xmit;
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unsigned long count = CIRC_CNT_TO_END(xmit->head,
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xmit->tail, UART_XMIT_SIZE);
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if (!count)
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return;
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if (count < sport->txfifo_size)
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writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
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sport->port.membase + UARTCR5);
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else {
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writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
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sport->port.membase + UARTCR5);
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lpuart_dma_tx(sport, count);
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}
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}
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static void lpuart_dma_tx_complete(void *arg)
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{
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struct lpuart_port *sport = arg;
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struct scatterlist *sgl = &sport->tx_sgl[0];
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struct circ_buf *xmit = &sport->port.state->xmit;
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unsigned long flags;
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async_tx_ack(sport->dma_tx_desc);
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spin_lock_irqsave(&sport->port.lock, flags);
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dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
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sport->dma_tx_in_progress = 0;
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sport->port.icount.tx += sport->dma_tx_bytes;
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sport->dma_tx_in_progress = false;
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spin_unlock_irqrestore(&sport->port.lock, flags);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&sport->port);
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lpuart_prepare_tx(sport);
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if (waitqueue_active(&sport->dma_wait)) {
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wake_up(&sport->dma_wait);
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return;
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}
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spin_lock_irqsave(&sport->port.lock, flags);
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if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
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lpuart_dma_tx(sport);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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}
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static int lpuart_dma_tx_request(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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struct dma_slave_config dma_tx_sconfig = {};
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int ret;
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dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
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dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma_tx_sconfig.dst_maxburst = 1;
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dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
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ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
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if (ret) {
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dev_err(sport->port.dev,
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"DMA slave config failed, err = %d\n", ret);
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return ret;
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}
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return 0;
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}
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static void lpuart_flush_buffer(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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if (sport->lpuart_dma_tx_use) {
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if (sport->dma_tx_in_progress) {
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dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
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sport->dma_tx_nents, DMA_TO_DEVICE);
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sport->dma_tx_in_progress = false;
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}
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dmaengine_terminate_all(sport->dma_tx_chan);
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sport->dma_tx_in_progress = 0;
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}
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}
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@ -469,8 +484,8 @@ static void lpuart_start_tx(struct uart_port *port)
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writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
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if (sport->lpuart_dma_tx_use) {
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if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
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lpuart_prepare_tx(sport);
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if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
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lpuart_dma_tx(sport);
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} else {
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if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
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lpuart_transmit_buffer(sport);
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@ -489,6 +504,29 @@ static void lpuart32_start_tx(struct uart_port *port)
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lpuart32_transmit_buffer(sport);
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}
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/* return TIOCSER_TEMT when transmitter is not busy */
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static unsigned int lpuart_tx_empty(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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unsigned char sr1 = readb(port->membase + UARTSR1);
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unsigned char sfifo = readb(port->membase + UARTSFIFO);
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if (sport->dma_tx_in_progress)
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return 0;
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if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
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return TIOCSER_TEMT;
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return 0;
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}
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static unsigned int lpuart32_tx_empty(struct uart_port *port)
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{
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return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
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TIOCSER_TEMT : 0;
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}
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static irqreturn_t lpuart_txint(int irq, void *dev_id)
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{
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struct lpuart_port *sport = dev_id;
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@ -662,12 +700,8 @@ static irqreturn_t lpuart_int(int irq, void *dev_id)
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if (sts & UARTSR1_RDRF)
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lpuart_rxint(irq, dev_id);
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if (sts & UARTSR1_TDRE) {
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if (sport->lpuart_dma_tx_use)
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lpuart_pio_tx(sport);
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else
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lpuart_txint(irq, dev_id);
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}
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if (sts & UARTSR1_TDRE)
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lpuart_txint(irq, dev_id);
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return IRQ_HANDLED;
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}
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@ -692,29 +726,6 @@ static irqreturn_t lpuart32_int(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/* return TIOCSER_TEMT when transmitter is not busy */
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static unsigned int lpuart_tx_empty(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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unsigned char sr1 = readb(port->membase + UARTSR1);
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unsigned char sfifo = readb(port->membase + UARTSFIFO);
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if (sport->dma_tx_in_progress)
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return 0;
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if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
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return TIOCSER_TEMT;
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return 0;
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}
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static unsigned int lpuart32_tx_empty(struct uart_port *port)
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{
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return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
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TIOCSER_TEMT : 0;
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}
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static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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{
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struct tty_port *port = &sport->port.state->port;
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@ -890,18 +901,6 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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return 0;
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}
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static void lpuart_dma_tx_free(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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sport->dma_tx_buf_bus = 0;
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sport->dma_tx_buf_virt = NULL;
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}
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static void lpuart_dma_rx_free(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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@ -1061,44 +1060,6 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport)
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lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
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}
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static int lpuart_dma_tx_request(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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struct dma_slave_config dma_tx_sconfig;
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dma_addr_t dma_bus;
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unsigned char *dma_buf;
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int ret;
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dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
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sport->port.state->xmit.buf,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
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dev_err(sport->port.dev, "dma_map_single tx failed\n");
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return -ENOMEM;
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}
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dma_buf = sport->port.state->xmit.buf;
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dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
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dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
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dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
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ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
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if (ret < 0) {
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dev_err(sport->port.dev,
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"Dma slave config failed, err = %d\n", ret);
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return ret;
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}
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sport->dma_tx_buf_virt = dma_buf;
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sport->dma_tx_buf_bus = dma_bus;
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sport->dma_tx_in_progress = 0;
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return 0;
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}
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static void rx_dma_timer_init(struct lpuart_port *sport)
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{
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setup_timer(&sport->lpuart_timer, lpuart_timer_func,
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@ -1151,6 +1112,7 @@ static int lpuart_startup(struct uart_port *port)
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}
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if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
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init_waitqueue_head(&sport->dma_wait);
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sport->lpuart_dma_tx_use = true;
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temp = readb(port->membase + UARTCR5);
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writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
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@ -1220,8 +1182,15 @@ static void lpuart_shutdown(struct uart_port *port)
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lpuart_dma_rx_free(&sport->port);
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}
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if (sport->lpuart_dma_tx_use)
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lpuart_dma_tx_free(&sport->port);
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if (sport->lpuart_dma_tx_use) {
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if (wait_event_interruptible(sport->dma_wait,
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!sport->dma_tx_in_progress) != false) {
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sport->dma_tx_in_progress = false;
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dmaengine_terminate_all(sport->dma_tx_chan);
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}
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lpuart_stop_tx(port);
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}
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}
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static void lpuart32_shutdown(struct uart_port *port)
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