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mmc: sdhci-acpi: Fix HS400 tuning for AMDI0040
The AMD eMMC Controller can only use the tuned clock while in HS200 and
HS400 mode. If we switch to a different mode, we need to disable the
tuned clock. If we have previously performed tuning and switch back to
HS200 or HS400, we can re-enable the tuned clock.
Previously the tuned clock was not getting disabled when switching to
DDR52 which is part of the HS400 tuning sequence.
Fixes: 34597a3f60
("mmc: sdhci-acpi: Add support for ACPI HID of AMD Controller with HS400")
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20200819125832.v2.1.Ie8f0689ec9f449203328b37409d1cf06b565f331@changeid
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
parent
9123e3a74e
commit
61d7437ed1
@ -535,6 +535,11 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
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.caps = MMC_CAP_NONREMOVABLE,
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.caps = MMC_CAP_NONREMOVABLE,
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};
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};
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struct amd_sdhci_host {
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bool tuned_clock;
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bool dll_enabled;
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};
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/* AMD sdhci reset dll register. */
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/* AMD sdhci reset dll register. */
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#define SDHCI_AMD_RESET_DLL_REGISTER 0x908
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#define SDHCI_AMD_RESET_DLL_REGISTER 0x908
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@ -555,24 +560,64 @@ static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host)
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}
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}
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/*
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/*
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* For AMD Platform it is required to disable the tuning
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* The initialization sequence for HS400 is:
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* bit first controller to bring to HS Mode from HS200
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* HS->HS200->Perform Tuning->HS->HS400
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* mode, later enable to tune to HS400 mode.
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*
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* The re-tuning sequence is:
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* HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
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*
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* The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
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* mode. If we switch to a different mode, we need to disable the tuned clock.
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* If we have previously performed tuning and switch back to HS200 or
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* HS400, we can re-enable the tuned clock.
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*
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*/
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*/
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static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
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struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
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unsigned int old_timing = host->timing;
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unsigned int old_timing = host->timing;
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u16 val;
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sdhci_set_ios(mmc, ios);
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sdhci_set_ios(mmc, ios);
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if (old_timing == MMC_TIMING_MMC_HS200 &&
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ios->timing == MMC_TIMING_MMC_HS)
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if (old_timing != host->timing && amd_host->tuned_clock) {
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sdhci_writew(host, 0x9, SDHCI_HOST_CONTROL2);
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if (host->timing == MMC_TIMING_MMC_HS400 ||
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if (old_timing != MMC_TIMING_MMC_HS400 &&
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host->timing == MMC_TIMING_MMC_HS200) {
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ios->timing == MMC_TIMING_MMC_HS400) {
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val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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sdhci_writew(host, 0x80, SDHCI_HOST_CONTROL2);
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val |= SDHCI_CTRL_TUNED_CLK;
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sdhci_acpi_amd_hs400_dll(host);
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sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
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} else {
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val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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val &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
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}
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}
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/* DLL is only required for HS400 */
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if (host->timing == MMC_TIMING_MMC_HS400 &&
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!amd_host->dll_enabled) {
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sdhci_acpi_amd_hs400_dll(host);
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amd_host->dll_enabled = true;
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}
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}
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}
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static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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int err;
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
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struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
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amd_host->tuned_clock = false;
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err = sdhci_execute_tuning(mmc, opcode);
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if (!err && !host->tuning_err)
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amd_host->tuned_clock = true;
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return err;
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}
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}
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static const struct sdhci_ops sdhci_acpi_ops_amd = {
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static const struct sdhci_ops sdhci_acpi_ops_amd = {
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@ -602,6 +647,7 @@ static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
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host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
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host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
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host->mmc_host_ops.set_ios = amd_set_ios;
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host->mmc_host_ops.set_ios = amd_set_ios;
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host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
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return 0;
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return 0;
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}
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}
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@ -613,6 +659,7 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
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SDHCI_QUIRK_32BIT_ADMA_SIZE,
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SDHCI_QUIRK_32BIT_ADMA_SIZE,
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.quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
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.quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
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.probe_slot = sdhci_acpi_emmc_amd_probe_slot,
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.probe_slot = sdhci_acpi_emmc_amd_probe_slot,
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.priv_size = sizeof(struct amd_sdhci_host),
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};
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};
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struct sdhci_acpi_uid_slot {
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struct sdhci_acpi_uid_slot {
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