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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 22:40:51 +07:00
[BNX2X]: fix MSI-X/INT#A errata
Errata A0.158 workaround. Running in INT#A mode after running with MSI-X fails due to a PCI core bug. Signed-off-by: Eliezer Tamir <eliezert@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -443,7 +443,7 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
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DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
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}
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static void bnx2x_enable_int(struct bnx2x *bp)
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static void bnx2x_int_enable(struct bnx2x *bp)
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{
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int port = bp->port;
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u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
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@ -456,18 +456,26 @@ static void bnx2x_enable_int(struct bnx2x *bp)
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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} else {
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val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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HC_CONFIG_0_REG_INT_LINE_EN_0 |
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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/* Errata A0.158 workaround */
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
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val, port, addr, msix);
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REG_WR(bp, addr, val);
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val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
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}
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) msi %d\n",
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
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val, port, addr, msix);
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REG_WR(bp, addr, val);
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}
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static void bnx2x_disable_int(struct bnx2x *bp)
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static void bnx2x_int_disable(struct bnx2x *bp)
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{
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int port = bp->port;
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u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
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@ -486,7 +494,7 @@ static void bnx2x_disable_int(struct bnx2x *bp)
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BNX2X_ERR("BUG! proper val not read from IGU!\n");
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}
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static void bnx2x_disable_int_sync(struct bnx2x *bp)
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static void bnx2x_int_disable_sync(struct bnx2x *bp)
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{
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int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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@ -494,7 +502,7 @@ static void bnx2x_disable_int_sync(struct bnx2x *bp)
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atomic_inc(&bp->intr_sem);
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/* prevent the HW from sending interrupts */
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bnx2x_disable_int(bp);
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bnx2x_int_disable(bp);
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/* make sure all ISRs are done */
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if (msix) {
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@ -5710,7 +5718,7 @@ static void bnx2x_nic_init(struct bnx2x *bp)
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bnx2x_init_internal(bp);
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bnx2x_init_stats(bp);
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bnx2x_init_ind_table(bp);
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bnx2x_enable_int(bp);
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bnx2x_int_enable(bp);
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}
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@ -7154,7 +7162,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
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napi_disable(&bnx2x_fp(bp, i, napi));
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int_disable:
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bnx2x_disable_int_sync(bp);
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bnx2x_int_disable_sync(bp);
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bnx2x_free_skbs(bp);
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bnx2x_free_irq(bp);
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@ -7174,7 +7182,7 @@ static void bnx2x_netif_stop(struct bnx2x *bp)
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bp->rx_mode = BNX2X_RX_MODE_NONE;
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bnx2x_set_storm_rx_mode(bp);
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bnx2x_disable_int_sync(bp);
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bnx2x_int_disable_sync(bp);
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bnx2x_link_reset(bp);
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for_each_queue(bp, i)
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