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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT (v2) drm/i915: no lvds quirk for AOpen MP45 drm/i915: Force explicit bpp selection for intel_dp_link_required drm/radeon: do not continue after error from r600_ib_test drivers/gpu/drm/drm_ioc32.c: initialize all fields drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT drm/i915:: Disable FBC on SandyBridge
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commit
612b8507c5
@ -315,7 +315,8 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd,
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if (err)
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return err;
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if (__get_user(c32.auth, &client->auth)
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if (__get_user(c32.idx, &client->idx)
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|| __get_user(c32.auth, &client->auth)
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|| __get_user(c32.pid, &client->pid)
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|| __get_user(c32.uid, &client->uid)
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|| __get_user(c32.magic, &client->magic)
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@ -1872,7 +1872,7 @@ static void intel_update_fbc(struct drm_device *dev)
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if (enable_fbc < 0) {
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DRM_DEBUG_KMS("fbc set to per-chip default\n");
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enable_fbc = 1;
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if (INTEL_INFO(dev)->gen <= 5)
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if (INTEL_INFO(dev)->gen <= 6)
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enable_fbc = 0;
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}
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if (!enable_fbc) {
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@ -5307,6 +5307,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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pipeconf &= ~PIPECONF_INTERLACE_MASK;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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/* the chip adds 2 halflines automatically */
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@ -5317,7 +5318,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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adjusted_mode->crtc_vsync_end -= 1;
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adjusted_mode->crtc_vsync_start -= 1;
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} else
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pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
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pipeconf |= PIPECONF_PROGRESSIVE;
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I915_WRITE(HTOTAL(pipe),
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(adjusted_mode->crtc_hdisplay - 1) |
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@ -5902,6 +5903,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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pipeconf &= ~PIPECONF_INTERLACE_MASK;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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/* the chip adds 2 halflines automatically */
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@ -5912,7 +5914,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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adjusted_mode->crtc_vsync_end -= 1;
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adjusted_mode->crtc_vsync_start -= 1;
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} else
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pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
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pipeconf |= PIPECONF_PROGRESSIVE;
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I915_WRITE(HTOTAL(pipe),
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(adjusted_mode->crtc_hdisplay - 1) |
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@ -208,17 +208,8 @@ intel_dp_link_clock(uint8_t link_bw)
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*/
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static int
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intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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struct drm_crtc *crtc = intel_dp->base.base.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int bpp = 24;
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if (check_bpp)
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bpp = check_bpp;
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else if (intel_crtc)
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bpp = intel_crtc->bpp;
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return (pixel_clock * bpp + 9) / 10;
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}
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@ -245,12 +236,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
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return MODE_PANEL;
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}
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mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
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mode_rate = intel_dp_link_required(mode->clock, 24);
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max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
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if (mode_rate > max_rate) {
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mode_rate = intel_dp_link_required(intel_dp,
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mode->clock, 18);
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mode_rate = intel_dp_link_required(mode->clock, 18);
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if (mode_rate > max_rate)
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return MODE_CLOCK_HIGH;
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else
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@ -683,7 +673,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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int lane_count, clock;
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int max_lane_count = intel_dp_max_lane_count(intel_dp);
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int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
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int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
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int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
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static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
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if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
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@ -701,7 +691,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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for (clock = 0; clock <= max_clock; clock++) {
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int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
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if (intel_dp_link_required(intel_dp, mode->clock, bpp)
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if (intel_dp_link_required(mode->clock, bpp)
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<= link_avail) {
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intel_dp->link_bw = bws[clock];
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intel_dp->lane_count = lane_count;
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@ -692,6 +692,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
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DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
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},
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "AOpen i45GMx-I",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
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DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
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},
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Aopen i945GTt-VFA",
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@ -3191,6 +3191,7 @@ static int evergreen_startup(struct radeon_device *rdev)
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if (r) {
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DRM_ERROR("radeon: failed testing IB (%d).\n", r);
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rdev->accel_working = false;
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return r;
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}
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r = r600_audio_init(rdev);
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