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igc: Add Receive Descriptor Minimum Threshold Count to clear HW counters

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The statistics of this register are being tracked, however, the register
was inadvertently missed when implementing igc_clear_hw_cntrs_base().
The register is clear on read, so add it to the function so that the
register is cleared when requested so the tracked count is accurate.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Sasha Neftin 2020-06-22 10:20:30 +03:00 committed by Tony Nguyen
parent d9f0c8e457
commit 60f7bb8241
1 changed files with 1 additions and 0 deletions
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drivers/net/ethernet/intel/igc/igc_mac.c
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@ -308,6 +308,7 @@ void igc_clear_hw_cntrs_base(struct igc_hw *hw)
rd32(IGC_TLPIC);
rd32(IGC_RLPIC);
rd32(IGC_HGPTC);
rd32(IGC_RXDMTC);
rd32(IGC_HGORCL);
rd32(IGC_HGORCH);
rd32(IGC_HGOTCL);